Prosecution Insights
Last updated: July 17, 2026
Application No. 18/404,831

Gate Patterning for Stacked Device Structure

Non-Final OA §112
Filed
Jan 04, 2024
Priority
Mar 24, 2023 — provisional 63/492,007
Examiner
HRNJIC, ADIN
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
66%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
73%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allowance Rate
38 granted / 58 resolved
-2.5% vs TC avg
Moderate +8% lift
Without
With
+7.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
27 currently pending
Career history
102
Total Applications
across all art units

Statute-Specific Performance

§103
93.3%
+53.3% vs TC avg
§102
3.5%
-36.5% vs TC avg
§112
3.2%
-36.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 58 resolved cases

Office Action

§112
Detailed Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 8, 12, and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on April 30th, 2026. Applicant's election with traverse of species 2 and 4 in the reply filed on April 30th, 2026, is acknowledged. The traversal is on the ground(s) that the office action attempts to identify species solely by reference to applicant’s claims, rather than by reference to applicant’s figures. This is not found persuasive because species 2 and species 4 are represented by the transition from figure 3N to figure 3O and paragraph [0058] of applicant’s filed specification. Similarly, species 1 and species 3 are represented by figure 4 and paragraph [0064] of applicant’s filed specification. The requirement is still deemed proper and is therefore made FINAL. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 16-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 16 recites the limitation “a terminal functional group” in line 5. It is unclear if this limitation refers to the terminal functional group defined in line 7 of Claim 10 or a second, different terminal functional group. For the purpose of examination, the limitation will be interpreted as “the terminal functional group”. Allowable Subject Matter Claims 1-7, 9-11, and 13-19 are allowed. The following is an examiner’s statement of reasons for allowance. None of the cited references, either singly or in combination, teach or render obvious the limitations presented in Claim 1 wherein “forming a dummy layer having a top surface that is below the second channel structure; selectively depositing a hard mask over the second gate dielectric, wherein deposition parameters of the selectively depositing and a composition of the dummy layer are configured to inhibit deposition of the hard mask on the top surface of the dummy layer; selectively removing the dummy layer; and selectively removing the hard mask after selectively removing the dummy layer”, in Claim 10 wherein “performing a spin-on deposition process to form a dummy layer that wraps the channel stack, wherein the dummy layer includes silicon, oxygen, and a terminal functional group that inhibits formation of metal nitride on the dummy layer; recessing the dummy layer below the first channel layer; selectively depositing a metal nitride mask over the first high-k dielectric layer; and after selectively removing the dummy layer, selectively removing the metal nitride mask”, and in Claim 18 wherein “forming a dummy layer that covers a first portion of the dipole dopant source layer and exposes a second portion of the dipole dopant source layer, wherein the first portion of the dipole dopant source layer is over the first gate dielectric, the second portion of the dipole dopant source layer is over the second gate dielectric, and the dummy layer includes silicon, oxygen, and a terminal functional group that inhibits formation of metal nitride on the dummy layer; removing the second portion of the dipole dopant source layer to expose the second gate dielectric around the second channel layer; forming a metal nitride mask over the exposed second gate dielectric, wherein the metal nitride mask wraps the second channel layer; after removing the dummy layer, removing the metal nitride mask”. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ge et al. (2021/0005604 A1) discloses masking lower channels in a stacked channel transistor. Cho et al. (2025/0218782 A1) discloses using reaction inhibition layers in forming a stacked channel transistor. Lin et al. (2022/0344354 A1) discloses using dipole layers to form multiple threshold voltages in a stack channel transistor. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADIN HRNJIC whose telephone number is (571)270-1794. The examiner can normally be reached Monday-Friday 8:00 AM - 4:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.H./Examiner, Art Unit 2817 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Jan 04, 2024
Application Filed
Jul 06, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
66%
Grant Probability
73%
With Interview (+7.8%)
3y 4m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 58 resolved cases by this examiner. Grant probability derived from career allowance rate.

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