DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/4/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract is consistent with the requirements set forth in the MPEP 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: METHOD FOR FORMING A MEMORY STRUCTURE
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 3-7 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chang US PGPub. 2023/0420264. Regarding claim 1, Chang teaches a method (fig. 2-4E) for forming a semiconductor structure (200, fig. 4E) [0033], comprising: providing a substrate (210, fig. 4A) [0034] having a memory array region (220, fig. 4A) [0034] and a peripheral region (230, fig. 4A) [0034] thereon; forming a memory structure (222/224, fig. 3-4A) [0037] on the substrate (210) within the memory array region (220), wherein a step height (H1, fig. 4A) [0039] is formed between the memory array region (220) and the peripheral region (230); blanketly depositing a dielectric layer (passivation layer 250a, fig. 4B) [0040] over the memory array region (220) and the peripheral region (230), wherein the dielectric layer (250a) covers the memory structure (222/224); performing a reverse etching process (P2, fig. 4C) [0043] to remove a portion (252, fig. 4C) of the dielectric layer (250a) from a central area (252, fig. 4C) of the memory array region (220), thereby forming an upwardly protruding wall structure (250b, fig. 4C) [0043] along a perimeter of the memory array region (220), wherein a remaining thickness (T5 + T3, fig. 4C) of the dielectric layer (250a) within the central area (252) of the memory array region (220) is equal to a combination of a polishing buffer thickness (T5, fig. 4C) [0068] and a target thickness (T3, fig. 4C) [0057]; subjecting the dielectric layer (250a) to a first polishing process (P3, fig. 4D) [0048] to remove the upwardly protruding wall structure (250b) from the memory array region (220) and remove an upper portion (T5, fig. 4C) of the dielectric layer (250a) having the polishing buffer thickness (T5, fig. 4C) from the memory array region (220), wherein a remainder (T3, fig. 4D) of the dielectric layer (250a) within the memory array region (220) has the target thickness (T3, fig. 4D) above the memory structure (222/224) (Chang fig. 3-4D). But Chang fails to teach two separate polishing steps, i.e., subjecting the dielectric layer (250a) to a first polishing process to remove the upwardly protruding wall structure (250b) from the memory array region (220); and subjecting the dielectric layer (250a) to a second polishing process to remove an upper portion (T5) of the dielectric layer (250a) having the polishing buffer thickness (T5) from the memory array region (220), wherein a remainder (T3) of the dielectric layer (250a) within the memory array region (220) has the target thickness (T3) above the memory structure (222/224). However, since Chang teaches a single continuous polishing step that results in the same and final target thickness (T3, fig. 4D) above the memory structure (222/224) as claimed first and second polishing processes, it would be obvious to one of ordinary skill in the art to separate the polishing process of Chang because it has also been held that selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results (see MPEP 2144.04.IV.C). Even further, MPEP2144.04.V.E states that continuous operation would be obvious in light of separate/batch processing in the prior art. In the instant case, the reverse is the case and would therefore be obvious that a separate/batch process including first and second polishing processes would be obvious in light of a continuous polishing process of the prior art/Chang. Regarding claim 3, Chang teaches the method according to claim 1, wherein the dielectric layer (250a) has a thickness (T1, fig. 4C) of 2000-2800nm [0039] but fails to teach wherein the dielectric layer (250a) has a thickness (T1) of 1500 to 2500 angstroms. However, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to use the thickness of the dielectric layer in the range as claimed so that the polishing time is within a rational time interval thereby preventing the polishing pad from deteriorating quickly as well as protecting the memory structures from removal during the polishing (Chang, [0071]), and because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05. Regarding claim 4, Chang teaches the method according to claim 3, wherein the remaining thickness (T5+T3, fig. 4C) of the dielectric layer (250a) within the central area (252) of the memory array region (220) is (T5, [0068] + T3=200-300nm, [0057]) but fails to teach wherein the remaining thickness of the dielectric layer within the central area of the memory array region is 500-600 angstroms. However, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to use the remaining thickness of the dielectric layer within the central area of the memory array region in the range as claimed so that the polishing time is within a rational time interval thereby preventing the polishing pad from deteriorating quickly as well as protecting the memory structures from removal during the polishing (Chang, [0071]), and because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05. Regarding claim 5, Chang teaches the method according to claim 3, wherein the remaining thickness (T5+T3, fig. 4C) of the dielectric layer (250a) within the central area (252) of the memory array region (220) is (T5, [0068] + T3=200-300nm, [0057]) but fails to teach wherein the remaining thickness of the dielectric layer within the central area of the memory array region is 550 angstroms. However, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to use the remaining thickness of the dielectric layer within the central area of the memory array region in the range as claimed so that the polishing time is within a rational time interval thereby preventing the polishing pad from deteriorating quickly as well as protecting the memory structures from removal during the polishing (Chang, [0071]), and because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05. Regarding claim 6, Chang teaches the method according to claim 5, wherein the polishing buffer thickness (T5, fig. 4C) is T2-H2-T3 [0068] (i.e. 2400-1433-250nm = 717nm, [0070]) but fails to teach wherein the polishing buffer thickness (T5, fig. 4C) is 250 to 350 angstroms. However, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to use the polishing buffer thickness in the range as claimed so that the polishing time is within a rational time interval thereby preventing the polishing pad from deteriorating quickly as well as protecting the memory structures from removal during the polishing (Chang, [0071]), and because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05. Regarding claim 7, Chang teaches the method according to claim 6, wherein the target thickness (T3, fig. 4C) is 200nm to 300nm [0057] but fails to teach wherein the target thickness is 200 to 300 angstroms. However, at the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to use the target thickness in the range as claimed so that the polishing time is within a rational time interval thereby preventing the polishing pad from deteriorating quickly as well as protecting the memory structures from removal during the polishing (Chang, [0071]), and because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05. Regarding claim 13, Chang teaches the method according to claim 1, wherein the dielectric layer (250a) has a thickness T (T1, fig. 4C) and the upwardly protruding wall structure (250b) has a height H (H2, fig. 4C), and wherein a ratio of the height H (H2 = 800-1400nm, [0045]) to the thickness T (T1=2000-2800nm, [0039]) is between ½ and ¾ (1400/2800 is ½) (Chang, fig. 4C, [0039], [0045]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to use the ratio of the height to the thickness in the range as claimed so that the polishing time is within a rational time interval thereby preventing the polishing pad from deteriorating quickly as well as protecting the memory structures from removal during the polishing (Chang, [0071]), and because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05.
Regarding claim 14, Chang teaches the method according to claim 13, wherein the remaining thickness (T5+T3) (T5, is T2-H2-T3; i.e. 2400-1433-250nm = 717nm, [0070] and T3 is 200nm to 300nm [0057]) of the dielectric layer (250a) within the central area (252) of the memory array region (220) ranges between ½ and ¼ of the thickness T (T1 = 2000-2800nm, [0039]) of the dielectric layer (250a) (Chang, fig. 4C, [0039], [0057]). T5+T3 of 717+300 is 1107 with is about ½ of 2000nm, the thickness of T1. At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to use the remaining thickness in the range as claimed so that the polishing time is within a rational time interval thereby preventing the polishing pad from deteriorating quickly as well as protecting the memory structures from removal during the polishing (Chang, [0071]), and because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05.
Regarding claim 15, Chang teaches the method according to claim 13, wherein the remaining thickness (T5+T3) (T5, is T2-H2-T3; i.e. 2400-1400-300nm = 700nm, where H2 is 800nm [0045] and T3 is 200nm to 300nm [0057]) of the dielectric layer within the central area (252) of the memory array region (220) is ⅓ of the thickness T (T1 = 2000-2800nm, [0039]) of the dielectric layer (250a) (Chang, fig. 4C, [0039], [0045], [0057]). T5+T3 of 700+300 is 1000 with is about ⅓ of 2800nm, the thickness of T1. At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in art to use the remaining thickness in the range as claimed so that the polishing time is within a rational time interval thereby preventing the polishing pad from deteriorating quickly as well as protecting the memory structures from removal during the polishing (Chang, [0071]), and because it has been held that where the general conditions of the claims are discloses in the prior art, it is not inventive to discover the optimum or workable range by routine experimentation. See MPEP 2144.05.
Claims 2 and 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Chang US PGPub. 2023/0420264 as applied to claim 1 above, and further in view of Kuo US PGPub. 2022/0158087. Regarding claim 2, Chang does not teach the method according to claim 1, wherein the dielectric layer (passivation layer 250a) comprises a low-k or ultra-low k dielectric material layer. However, Kuo teaches a method of manufacturing a semiconductor device (100, fig. 10) wherein the dielectric layer (206, fig. 10)[0024] comprises a low-k or ultra-low k dielectric material layer [0024] (Kuo, fig. 20, [0024]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make the simple substitution of the passivation material of Chang with the low-k dielectric material of Kuo because low-k materials are well known in the art and such substitution is art recognized equivalence (as insulating materials) for the same purpose to obtain predictable results such as preventing shorts (see MPEP 2144.06). Regarding claim 8, Chang does not teach the method according to claim 1, wherein the memory structure (222/224) comprises a conductive via embedded in a first intermediate dielectric layer, a memory storage structure embedded in a second intermediate dielectric layer, and a protective layer covering a sidewall of the memory storage structure and the first intermediate dielectric layer. However, Kuo teaches a method (fig. 1-10) of forming a semiconductor structure (100, fig. 10) [0036] wherein the memory structure (330, fig. 9-10) [0020] comprises a conductive via (208, fig. 10) [0017] embedded in a first intermediate dielectric layer (204, fig. 10) [0012], a memory storage structure (MTJ 304, fig. 10) [0018] embedded in a second intermediate dielectric layer (portion of 206 in region 16, fig. 10; hereinafter called 206’) [0024], and a protective layer (402, fig. 10) [0022] covering a sidewall of the memory storage structure (304) and the first intermediate dielectric layer (204) (Kuo, fig. 9-10). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to substitute the memory structure of Chang with the MTJ memory structure of Kuo because MTJ memory devices are well known in the art and such structure is art recognized and suitable for the intended purpose of producing a memory device with low power consumption, high integrity and durability (Kuo, [0002]) (see MPEP 2144.07).
Regarding claim 9, Chang in view of Kuo teaches the method according to claim 8, wherein the memory storage structure (330) comprises a magnetic tunneling junction (MTJ) structure (304, fig. 10) [0018] situated directly on the conductive via (208) (Kou, fig. 10). Regarding claim 10, Chang in view of Kuo teaches the method according to claim 8, wherein the conductive via (208) comprises a tungsten via [0017] (Kuo, fig. 10, [0017]).
Regarding claim 11, Chang in view of Kuo teaches the method according to claim 8, wherein the first intermediate dielectric layer (204) extends onto the peripheral region (14, fig. 10) (Kuo, fig. 10).
Regarding claim 12, Chang in view of Kuo teaches the method according to claim 11, wherein the dielectric layer (206, fig. 10) [0024] is in direct contact with the first intermediate dielectric layer (204) within the peripheral region (16) (Kuo, fig. 10).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Huo et al. US PGPub. 2022/0238800 teaches a method of forming an memory structure including a magnetic tunneling junction.
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892