DETAILED ACTION
This Office Action is in response to Restriction/Election, filed on 12/30/2025, on the application filed on 01/04/2024. Claims 11-20 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected Group I. Election was made without traverse in the reply filed on 12/30/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 11 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US20230309240A1 and Chen hereinafter).
Regarding claim 11, Chen discloses a manufacturing method of a circuit board structure (Figs. 3J-3L and ¶[0092-0094_0096_0100 & 0102-0103 show and indicates the manufacturing method of circuit board structure of Fig. 3L), comprising: providing a core layer, the core layer has a first surface and a second surface opposite to each other and comprises at least one dielectric portion and at least one metal portion (items 101, 1022, 1044 of Fig. 3J and ¶[0092-0094] show and indicates providing core layer 101; where core layer 101 has first surface 101-top-surface and second surface 101-bottom-surface opposite to each other and comprised of dielectric portion 1022 {insulating pillars 1022} and at least one metal portion 1014 {metal layer 1014 and the insulating pillars 1022 together form a second conductive post layer}); electroplating at least one electroplating metal layer on at least one of the first surface and the second surface of the core layer, the at least one electroplating metal layer exposes a portion of at least one of the first surface and the second surface and is at least connected to the at least one metal portion (items 2011, 3011 of Fig. 3K and ¶[0096 & 0100] show and indicates electroplating electroplating metal layers 2011 & 3011 {electroplating the fifth feature pattern and the sixth feature pattern, respectively, to form the first circuit layer 2011 and the second circuit layer 3011} on first surface 101-top-surface and second surface 101-bottom-surface, respectively, of core layer 101; where electroplating metal layers 2011 & 3011 exposes a portion of first surface 101-top-surface and second surface 101-bottom-surface, respectively, and connected to metal portion 1014 {first circuit layer 2011 and the second circuit layer 3011 are conductively connected through the second conductive post layer, which in turn is formed by metal layer 1014 and the insulating pillars 1022 together}); laminating at least one dielectric layer on at least one of the first surface and the second surface of the core layer and on the at least one electroplating metal layer (items 2012, 3012 of Fig. 3K and ¶[0102] show and indicates laminating dielectric layers 201 & 301 {first adding layer 201 and second adding layer 301} on first surface 101-top-surface and second surface 101-bottom-surface, respectively, of core layer 101 and on electroplating metal layers 2011 & 3011, respectively); performing the drilling process on dielectric layers 201 & 301 to form at least one opening that exposes a portion of the at least one electroplating metal layer (items 2012, 3012 of Fig. 3K and ¶[0102-0103] shows and indicates performing a drilling process on dielectric layer 201 & 301 {laser drilling in the first adding layer 201 and second adding layer 301 to form the first copper post layer 2012 and second copper post layer 3012} to form openings 2012-opening & 3012-opening {opening to form first copper post layer 2012 and opening to form second copper post layer 3012}, respectively, that exposes portions of electroplating metal layers 2011 & 3011); and forming at least one conductive metal layer in the at least one opening of the at least one dielectric layer, and the at least one conductive metal layer is correspondingly connected to the at least one electroplating metal layer (items 2012, 3012 of Fig. 3K and ¶[0102] shows and indicates forming conductive metal layer 2012 {first copper post layer 2012} in openings 2012-opening of dielectric layer 201; forming conductive metal layer 3012 {second copper post layer 3012} in openings 3012-opening of dielectric layer 301; where conductive metal layer 3012 is correspondingly connected to electroplating metal layers 3011).
Allowable Subject Matter
Claims 12-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 12, the primary reason for allowance is due to a manufacturing method of the circuit board structure, wherein the at least one dielectric portion is a plurality of dielectric portions, and the at least one metal portion comprises a metal portion, and the step of providing the core layer comprises: providing a copper plate having the first surface and the second surface, wherein a thickness of the copper plate is greater than or equal to 200 μm and less than or equal to 500 μm; performing a first half etching process on the first surface of the copper plate to form a plurality of first cavities on the first surface; filling a first dielectric paste in the first cavities; performing a second half-etching process on the second surface of the copper plate to form a plurality of second cavities on the second surface and in communication with the first cavities to define the metal portion, wherein the second cavities expose the first dielectric paste; and filling a second dielectric paste in the second cavities, and the second dielectric paste is connected to the first dielectric paste to define the dielectric portions.
Regarding claims 13 and 16, the primary reason for allowance is due to the dependency on claim 12.
Regarding claims 14 and 15, the primary reason for allowance is due to the dependency on claims 13 and 12.
Regarding claim 18, the primary reason for allowance is due to a manufacturing method of the circuit board structure, further comprising: the at least one dielectric portion is a dielectric portion, the at least one metal portion comprises a first metal portion and a second metal portion, and the at least one electroplating metal layer is connected to the first metal portion; laminating the at least one dielectric layer and at least one first copper foil layer thereon on at least one of the first surface and the second surface of the core layer and on the at least one electroplating metal layer; performing a drilling process on the at least one dielectric layer and the at least one first copper foil layer thereon to form the at least one opening, the at least one opening comprises a first opening and a second opening, the first opening exposes a portion of the at least one electroplating metal layer, the second opening exposes a portion of the second metal portion; forming at least one first electroplating seed layer on the at least one first copper foil layer and in the first opening and the second opening; forming at least one first patterned photoresist layer on the at least one first electroplating seed layer, the at least one first patterned photoresist layer exposes a portion of the at least one electroplating seed layer located on the at least one first copper foil layer and the at least one first electroplating seed layer located in the first opening and the second opening; with the at least one first patterned photoresist layer as an electroplating mask, electroplating a first metal material on the at least one first electroplating seed layer exposed by the at least one first patterned photoresist layer; and removing the at least one first patterned photoresist layer to form the at least one conductive metal layer in the first opening and the second opening correspondingly connected to the at least one electroplating metal layer and the second metal portion, and extending to the at least one dielectric layer.
Regarding claim 19, the primary reason for allowance is due to the dependency on claim 18.
Regarding claim 20, the primary reason for allowance is due to the dependency on claims 19 and 18.
Conclusion
The FOLLOWING PRIOR ART are made of record and not relied upon, but considered pertinent to applicant's method independent claim 11:
Lin et al. (CN 101677068 A).
Chen et al. (CN 109673099 A).
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847