DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/10/2025 was filed before the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Meunier-Berillard et al. (2009/0072351).
Re claim 1, Meunier-Berillard teaches a hybrid SOI substrate (Figs. 1-10), comprising: a semiconductor substrate (11), wherein the semiconductor substrate (11) includes a first region (annotated Fig. 10, shown below) and a second region (annotated Fig. 10, shown below); an upper semiconductor layer (annotated Fig. 10, shown below) in the first region (annotated Fig. 10, shown below), wherein the upper semiconductor layer (annotated Fig. 10, shown below) is separated from the semiconductor substrate by a cavity (annotated Fig. 10, shown below); and a bulk semiconductor layer (annotated Fig. 10, shown below) over the semiconductor substrate (11) in the second region (annotated Fig. 10, shown below), wherein the bulk semiconductor layer (annotated Fig. 10, shown below) extends from a height below the cavity (annotated Fig. 10, shown below) to a height of an upper surface of the upper semiconductor layer (annotated Fig. 10, shown below).
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Claim(s) 5, 15 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Meunier-Berillard et al. (2009/0072351).
Re claim 5, Meunier-Berillard a method of manufacturing an integrated circuit device (Figs. 1-10), the method comprising: forming a sacrificial layer (16) over a semiconductor body (11) that comprises a first region (upper) and a second region (lower); epitaxially growing [22] an upper semiconductor layer (2) over the sacrificial layer (16); forming a mask over the first region [23]; etching through the upper semiconductor layer and the sacrificial layer in the second region while the first region is masked [23]; epitaxially growing a bulk semiconductor layer (7) in the second region (lower); etching holes, wherein the sacrificial layer is exposed through the holes [23-27]; etching the sacrificial layer through the holes so as to form a cavity beneath the upper semiconductor layer in the first region [23-27]; and sealing the holes with dielectric [27-34].
Re claim 15, Meunier-Berillard teaches the method of claim 5, wherein the holes are at a periphery of the first region (Fig. 9).
Re claim 20, Meunier-Berillard teaches the method of claim 5, wherein a process of sealing the holes with dielectric fills the cavity with dielectric [27].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Meunier-Berillard et al. (2009/0072351) in view of the following reasons.
Re claim 3, Meunier-Berillard teaches an integrated circuit device (Figs. 1-10), comprising: a semiconductor substrate (11), wherein the semiconductor substrate (11) includes a first region (annotated Fig. 10, shown below) and a second region (annotated Fig. 10, shown below); an upper semiconductor layer (annotated Fig. 10, shown below)over the first region (annotated Fig. 10, shown below); an insulating layer (15) between the upper semiconductor layer (annotated Fig. 10, shown below) and the semiconductor substrate (11) in the first region (annotated Fig. 10, shown below); a bulk semiconductor layer (annotated Fig. 10, shown below) over the semiconductor substrate (11) in the second region (annotated Fig. 10, shown below), wherein the bulk semiconductor layer (annotated Fig. 10, shown below) is at heights equivalent with the insulating layer (annotated Fig. 10, shown below) and the upper semiconductor layer (annotated Fig. 10, shown below). Meunier-Berillard does not explicitly teach a polycrystalline semiconductor structure between the upper semiconductor layer and the bulk semiconductor layer at a side of the first region.
However, Applicant has not shown wherein a polycrystalline semiconductor structure between the upper semiconductor layer and the bulk semiconductor layer at a side of the first region has a specific, disclosed criticality that is unexpected and would not have been determined through routine experimentation of one having ordinary skill in the art. Therefore, it would have been obvious to have a polycrystalline semiconductor structure so as to customize, optimize, or otherwise meet customer space and design requirements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
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Allowable Subject Matter
Claims 2, 4, 6-14, 16 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 2, Meunier-Berillard teaches the hybrid SOI substrate of claim 1, further comprising a dielectric via that extends through a thickness of the upper semiconductor layer (Fig. 10), yet remains explicitly silent to wherein the dielectric via is continuous with and is of a same composition as a dielectric that lines the cavity. Re claim 4, Meunier-Berillard teaches the integrated circuit device of claim 3, yet remains explicitly silent to wherein: the semiconductor substrate comprises a semiconductor body and an undoped semiconductor layer disposed over the semiconductor body; and the undoped semiconductor layer has a lower concentration of crystal-originated particles than does the semiconductor body.
Re claim 6, Meunier-Berillard teaches the method of claim 5, yet remains explicitly silent to further comprising planarizing so that the bulk semiconductor layer in the second region is coplanar with the upper semiconductor layer in the first region.
Re claim 7, Meunier-Berillard teaches the method of claim 5, yet remains explicitly silent to wherein the semiconductor body is a high resistivity substrate.
Re claim 8, Meunier-Berillard teaches the method of claim 5, yet remains explicitly silent to further comprising epitaxially growing an undoped semiconductor layer over the semiconductor body prior to forming the sacrificial layer.
Claim 9 is objected to for at least depending from objected claim 8.
Re claim 10, Meunier-Berillard teaches the method of claim 5, yet remains explicitly silent to wherein polycrystalline semiconductor grows from an edge of the first region while epitaxially growing the bulk semiconductor layer in the second region. Claims 11 and 12 are objected to for at least depending from objected claim 10. Re claim 13, Meunier-Berillard teaches the method of claim 5, wherein forming the sacrificial layer comprises epitaxially growing the sacrificial layer, and the sacrificial layer is heavily doped. Re claim 14, Meunier-Berillard teaches the method of claim 5, yet remains explicitly silent to wherein etching the sacrificial layer comprises etching with a mixture of hydrofluoric, acetic, and nitric acids.
Re claim 16, Meunier-Berillard teaches the method of claim 5, yet remains explicitly silent to wherein etching the holes comprises: forming a second mask; forming first openings in the second mask in the first region; forming second openings in the second mask in the second region; and etching through the first openings to form the holes and etching through the second openings to form trenches.
Claims 17-19 are objected to for at least depending from objected claim 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hwang et al. (2023/0187267), Figs. 2-15; Rana et al. (2023/0096544), Figs. 1-8; Rana et al. (2022/0190108), Figs. 1-15; Ghyselen (2021/0132002), Figs. 1a-3d; Lin et al. (2020/0144369), Figs. 1-15; Adusumilli et al. (2019/0312142), Figs. 1A-10B; Liu et al. (2019/0081138), Figs. 1-5; Goktepeli (2018/0083098), Figs. 1-3. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
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