Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I, Species E(Figs. 3A-3R, claims 16-35) in the reply filed on 04/27/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/05/2024, 03/27/2025 and 03/31/2026. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16-17, 20-23 and 28-29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 2022/0336612).
As for claims 16 and 21, Chang et al. disclose in Fig. 2A-2Q and the related text a method comprising:
forming a semiconductor fin on a top surface of a semiconductor substrate 102 (fig. 2A), wherein the semiconductor fin comprises first semiconductor layers 105/107 and second semiconductor layers 119/122 alternately arranged (Fig. 2A, [0037]);
forming a recess 140 through the semiconductor fin and into the semiconductor substrate (Fig. 2B, [0048]);
forming a bottom epitaxial layer 152 in the recess (Fig. 2D, [0051]);
forming a bottom dielectric layer 156/112 in the recess (Fig. 2D-2H, [0051]-[0057]), wherein the bottom dielectric layer 112 partially covers a semiconductor surface below the top surface of the semiconductor substrate 102 (Fig. 2H); and
growing an epitaxial source/drain region 110 over the bottom dielectric layer (Fig. 2J, [0068]), wherein the epitaxial source/drain region is in (electrically/thermally) contact with a portion of the semiconductor surface below the top surface of the semiconductor substrate (Fig. 2J), and wherein the epitaxial source/drain region 110 is (electrically/thermally) connected to the bottom epitaxial layer 152.
As for claim 17, Chang et al. disclose the method of claim 16, further comprising: growing a bottom epitaxial layer 152 in the recess, wherein the bottom dielectric layer 112 is formed on the bottom epitaxial layer 152 (Fig. 2E, [0051]).
As for claim 20, Chang et al. disclose the method of claim 17, wherein a top (bottom) surface of the bottom epitaxial layer 152 is below the top surface of the semiconductor substrate 102, and sidewalls of the recess are exposed between the bottom dielectric layer 112 and the top surface of the semiconductor substrate 102 (Fig. 2I), and growing an epitaxial source/drain region comprises: growing a first source/drain layer from the sidewalls of the recess.
As for claim 22, Chang et al. disclose the method of claim 21, wherein the semiconductor channel comprises two or more semiconductor channel layers 107/120 stacked over a top surface of the semiconductor substrate 102.
As for claim 23, Chang et al. disclose the method of claim 22, wherein the bottom epitaxial layer 152 is disposed below the top surface of the semiconductor substrate (Fig. 2I), and a bottom section of the epitaxial source/drain region 152 is formed over the semiconductor substrate (Fig. 2I).
As for claim 28, Chang et al. disclose the method of claim 23, wherein the epitaxial source/drain region 110 is in (thermally/electrically) contact with the semiconductor substrate 102 on a sidewall below the top surface of the semiconductor substrate 102 and above the bottom dielectric layer 112 (fig. 2I).
As for claim 29, Chang et al. disclose the method of claim 22, further comprising forming inner spacers 148 disposed between the two or more semiconductor channel layers 107/120, wherein a top surface, a bottom surface and a sidewall of the inner spacer are in contact with the epitaxial source/drain region 110 (Fig. 2J).
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 30, 32 and 34 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang et al. (US 2023/0026310) .
The applied reference has a common assignees with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
As for claim 30, Chang et al. disclose in Fig. 2A-1–2V-2 and the related text a method, comprising:
forming a semiconductor stack 110/112 over a top surface of a semiconductor substrate 102 (Fig. 2A-1, [0017]), wherein the semiconductor stack comprises two or more semiconductor channel layers 112 and two or more sacrificial channel layers 110 vertically stacked above the top surface of the semiconductor substrate (Fig. 2A-1-2D-1);
forming a semiconductor fin 104 from the semiconductor stack (Fig 2D-1, [0054]);
forming a recess 140 through the semiconductor fin and into the semiconductor substrate (FIG. 2D-1, [0054]);
etching back end portions of the two or more sacrificial semiconductor layers 110 (FIG. 2E-1, [0057]);
forming two or more inner spacers 146 disposed alternately stacked with the two or more semiconductor channel layers (FIG. 2F-1, [0060]);
forming a bottom dielectric layer 152 in the recess (Fig. 2J-1, [0072]); and
forming an epitaxial source/drain region 154 in the recess [0076], wherein the epitaxial source/drain region comprises:
a first epitaxial source/drain layer 158 grown from the two or more semiconductor channel layers 112 and a semiconductor surface disposed under the top surface of the semiconductor substrate (Fig. 2k-1, [0076]); and
a bulk epitaxial source/drain layer 160 grown from the first epitaxial source/drain layer (Fig. 2J-2K-1, [0076]-[0077]).
As for claim 32, Chang et al. disclose the method of claim 30, further comprising: forming a bottom epitaxial layer 148 in the recess prior to forming the bottom dielectric layer 152 (FIG. 2H-1, [0065]).
As for claim 34, Chang et al. disclose the method of claim 31, further comprising: performing a recess etching process to etch back the two or more semiconductor channel layers and the side surface of the semiconductor substrate from the inner spacers (FIG. 2E-1, [0057]).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 30 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. in view of Wallace et al. (US 2024/0063274).
As for claim 30, Chang et al. disclose in Fig. 2A- and the related text a method, comprising:
forming a semiconductor stack over a top surface of a semiconductor substrate, wherein the semiconductor stack comprises two or more semiconductor channel layers 107 and two or more sacrificial channel layers 120 vertically stacked above the top surface of the semiconductor substrate (Fig. 2A-2B, [0049]);
forming a semiconductor fin from the semiconductor stack (Fig. 2B);
forming a recess 140 through the semiconductor fin and into the semiconductor substrate (Fig. 2B, [0048]);
etching back end portions of the two or more sacrificial semiconductor layers 120 (Fig. 2C, [0049]);
forming two or more inner spacers 148 disposed alternately stacked with the two or more semiconductor channel layers (Fig. 2C, [0050]);
forming a bottom dielectric layer 156/112 in the recess (Figs. 2D-2H, [0052]-[0059]); and
forming an epitaxial source/drain region 110 in the recess (Fig. 2J, [0068]),
wherein the epitaxial source/drain region 110 comprises:
a first epitaxial source/drain layer grown from the two or more semiconductor channel layers 107 and a semiconductor surface disposed under the top surface of the semiconductor substrate (Fig. 2J, [0068]); and
Chang et al. do not disclose a bulk epitaxial source/drain layer grown from the first epitaxial source/drain layer.
Wallace et al. teach in Fig. and the related a bulk epitaxial source/drain layer 135/136 grown from the first epitaxial source/drain layer [0038].
Chang et al. and Wallace et al. are analogous art because they both are directed transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Chang et al. to include bulk epitaxial source/drain layer as taught by Wallace et al., in order to reduce epi resistivity (Wallace [0038]).
As for claim 32, Chang et al. disclose the method of claim 30, further comprising: forming a bottom epitaxial layer 152 in the recess prior to forming the bottom dielectric layer 112 (Fig. 2D-2E).
Allowable Subject Matter
Claims 18-19, 24-27, 31, 33 and 35 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
“forming the bottom dielectric layer comprises: depositing a continuous dielectric layer; and forming an opening through the continuously dielectric layer to expose a portion of the bottom epitaxial layer, wherein a portion of the epitaxial source/drain region is grown from the bottom epitaxial layer through the opening”, as recited in claim 18. Claim 19 depends among objected claim 18;
“wherein the bottom dielectric layer includes an opening, and the bottom section of the epitaxial source/drain region extends below the bottom dielectric layer through the opening to contact the bottom epitaxial layer”, as recited in claim 24. Claims 25-27 depend among objected claim 24;
“the first epitaxial source/drain layer comprises: two or more channel sections 158 grown from the two or more semiconductor channel layers (Fig. 2K-1); and a bottom section grown from a side surface of the semiconductor substrate disposed under the top surface of the semiconductor substrate”, as recited in claim 31; and
“forming an opening through the bottom dielectric layer, wherein the first epitaxial source/drain layer comprises: two or more channel sections grown from the two or more semiconductor channel layers; and a bottom section grown from the bottom epitaxial layer through the opening of the bottom dielectric layer”, as recited in claim 33. Claim 35 depends among objected claim 33.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TRANG Q TRAN/Primary Examiner, Art Unit 2811
Prosecution Insights