DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsu et al (US Publication No. 2025/0219031).
Regarding claim 1, Hsu discloses a semiconductor package structure, comprising: a first substrate Fig 5, S; a capacitor structure disposed over the first substrate and comprising: a semiconductor substrate Fig 5, 10 having a first surface and a second surface opposite the first surface; a first capacitor Fig 2, 12 or Fig 5, 12 disposed on the first surface of the semiconductor substrate Fig 2 and Fig 5; and a second capacitor Fig 2, 22 or Fig 5, 22 disposed on the second surface of the semiconductor substrate Fig 2 and Fig 5; and a plurality of first conductive connectors Fig 5, 29 disposed over the capacitor structure and electrically coupled to the first capacitor; and a plurality of second conductive connectors Fig 5, 29 disposed below the capacitor structure and electrically coupled to the second capacitor Fig 2 and Fig 5.
Regarding claim 2, Hsu discloses, wherein the capacitor structure further comprises: a first metal layer Fig 5, 16 disposed between the semiconductor substrate and the first capacitor and electrically coupled to one of the first conductive connectors; and a second metal layer Fig 5, 26 disposed over a top surface of the first capacitor and electrically coupled to another one of the first conductive connectors Fig 5.
Regarding claim 3, Hsu discloses wherein the capacitor structure further comprises: a dielectric layer Fig 5, 14 disposed on the first surface of the semiconductor substrate and surrounding the first metal layer, the first capacitor, and the second metal layer Fig 5.
Regarding claim 5, Hsu discloses wherein the first capacitor vertically overlaps the second capacitor Fig 5.
Regarding claim 6, Hsu discloses wherein the first conductive connectors and the second conductive connectors each comprises microbumps, wire bonds, copper pillar bumps, or a combination thereof Fig 5.
Regarding claim 7, Hsu discloses a second substrate Fig 5, 40 disposed over the capacitor structure and electrically coupled to the first substrate through a plurality of conductive terminals, wherein the capacitor structure is disposed between the plurality of conductive terminals; and a semiconductor die disposed over the second substrate¶0031-0033, 0041 Fig 5.
Regarding claim 8, Hsu discloses wherein the first conductive connectors are electrically coupled to the second substrate and the second conductive connectors are electrically coupled to the first substrate Fig 5.
Claims 9-11, 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi (US Publication No. 2020/0294889).
Regarding claim 9, Choi discloses a semiconductor package structure, comprising: a substrate Fig 4, 600; a redistribution layer Fig 4, 310B/320B disposed over the substrate; a capacitor structure disposed over the redistribution layer and electrically coupled to the redistribution layer Fig 4, wherein the capacitor structure comprises: a semiconductor substrate Fig 2 or 4, 220 ¶0024; a first capacitor Fig 2 or 4, 230 disposed over the semiconductor substrate; and a second capacitor Fig 2 or 4, 230 disposed below the semiconductor substrate Fig 2 or 4, 220 and vertically overlapping the first capacitor; and a first semiconductor die Fig 4, 100 disposed over the redistribution layer Fig 4, 310B/320B and electrically coupled to the redistribution layer Fig 4.
Regarding claim 10, Choi discloses wherein the first semiconductor die Fig 4, 100T is disposed over the capacitor structure and electrically coupled to the first capacitor, and the redistribution layer is electrically coupled to the second capacitor Fig 4.
Regarding claim 11, Choi discloses a conductive pillar adjacent to the capacitor structure and electrically coupling the first semiconductor die to the redistribution layer Fig 4.
Regarding claim 17, Choi discloses a semiconductor package structure, comprising: a substrate Fig 4, 600; a semiconductor die Fig 4, 100 disposed over the substrate; a capacitor structure disposed between the substrate and the first semiconductor die Fig 4 and comprising: a semiconductor substrate Fig 2 or 4, 220 ¶0024; a first capacitor Fig 2 or 4, 230 disposed over the semiconductor substrate and electrically coupled to the first semiconductor die; and a second capacitor Fig 2 or 4, 230 disposed below the semiconductor substrate and electrically coupled to the substrate, wherein the first capacitor vertically overlaps the second capacitor Fig 4.
Regarding claim 18, Choi discloses a conductive pillar disposed over the substrate and electrically coupling the semiconductor die to the substrate; and a plurality of conductive terminals disposed below the substrate Fig 4.
Regarding claim 19, Choi discloses a first conductive connector electrically coupling the first capacitor to the first semiconductor die; and a second conductive connector electrically coupling the second capacitor to the substrate Fig 4.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al (US Publication No. 2025/0219031) in view of Ye et al (US Publication No. 2024/0072022).
Regarding claim 4, Hsu discloses all the limitations but silent on the length of the second metal layer. Whereas Ye discloses wherein a length of the first metal layer is greater than a length of the second metal layer Fig 3. Hsu and Ye are analogous art because they are directed to capacitor structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsu because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the metal layer length to improve connectivity.
Claims 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US Publication No. 2020/0294889) in view of Ye et al (US Publication No. 2024/0072022).
Regarding claim 12, Choi discloses wherein the capacitor structure is disposed over the first semiconductor die Fig 4, 100B and electrically coupled to the first semiconductor die Fig 4. Choi discloses all the limitations but silent on the type of bonding. Whereas Ye discloses a capacitor structure coupled to the semiconductor die through a first wire bond Fig 5. Choi and Ye are analogous art because they are directed to capacitor structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Choi because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the type of connection between devices as an alternative method known in the art as a matter of design choice.
Regarding claim 13, Ye discloses a second semiconductor die disposed over the first semiconductor die and electrically coupled to the first semiconductor die through a second wire bond Fig 5.
Regarding claim 14, Ye discloses wherein the first semiconductor die is electrically coupled to the redistribution layer through a second wire bond ¶0026 Fig 3-4 and Fig 8A.
Regarding claim 15, Choi discloses wherein the capacitor structure is adjacent to the first semiconductor die, wherein the capacitor structure and the first semiconductor die are electrically coupled to the redistribution layer Fig 4. Choi discloses all the limitations but silent on the type of bonding. Whereas Ye discloses a capacitor structure coupled to the semiconductor die through a first wire bond Fig 5. Choi and Ye are analogous art because they are directed to capacitor structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Choi because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the type of connection between devices as an alternative method known in the art as a matter of design.
Regarding claim 16, Choi discloses a second semiconductor die disposed over the redistribution layer and electrically coupled to the capacitor structure and the first semiconductor die Fig 4. Choi discloses all the limitations but silent on the type of bonding. Whereas Ye discloses a capacitor structure coupled to the semiconductor die through a first wire bond Fig 5. Choi and Ye are analogous art because they are directed to capacitor structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Choi because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the type of connection between devices as an alternative method known in the art as a matter of design
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US Publication No. 2020/0294889) in view of Ye et al (US Publication No. 2024/0072022) and in further view of Kung et al (US Publication No. 2023/0065615).
Regarding claim 20, Choi discloses all the limitations but silent on the connector/pillar arrangement. Whereas Kung discloses wherein a height of the conductive pillar is equal to a total height of the first conductive connector, the capacitor structure, and the second conductive connector Fig 2. Choi and Kung are analogous art because they are directed to capacitor structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Choi because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the connector arrangement and incorporate the teachings of Kung as an alternative arrangement to improve device connectivity.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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