DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I, Species A, and Species y, in the reply filed on 4/23/2026 is acknowledged.
Claim 5 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/23/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 3, 4, 6-7, 9, 15, 22, 23, and 25 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 3, the limitation “forming the second gate stack to surround the plurality of second nanostructures,” is unclear as to how it is related to the same recitation of claim 1.
Regarding claim 4, the limitation “a plan view” is unclear as to how it is related to the plan view recited in claim 1.
Regarding claim 9, the limitation “patterning the first lower fin element to form an opening exposing a bottom of the source/drain feature; and forming a contact plug in the opening,” is unclear as to how it is combinable with the features of the elected invention. In particular, the only disclosure of a back side contact to a source/drain features appears to be in embodiment of Fig. 14, however applicant has elected Fig. 4. It is unclear how a back side contact would be combined with the front side contacts of elected invention of Fig. 4.
Regarding claim 15, the limitation “surrounding the channel layers the first fin structure and the second fin structure,” appears to have a grammatical/typographical error which renders the limitation unclear.
Regarding claim 22, the claim is indefinite for depending on a cancelled claim.
Regarding claim 23, the limitation “the connecting wall,” is unclear because it lacks proper antecedent basis.
Regarding claim 25, the limitations “the source/drain terminal of the first pull-down transistor and the pass-gate transistor share a source/drain feature,” is unclear because “the source/drain terminal,” “the first pull-down transistor,” and “the pass-gate transistor” each lack proper antecedent basis. It is further unclear because it is unclear as to what shares a source/drain feature and as to how the shared source/drain feature is related to the previously recited source/drain feature.
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4, 7-15, 21-22, and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bentum et al. (US 20140078817; herein “Bentum”) in view of Liaw (US 20220093612; herein “Liaw”).
Regarding claim 1, Bentum discloses in Fig. 2 and related text a method for forming a semiconductor structure, comprising:
forming a first active region (e.g. active region of 14 and 18, see [0014]), wherein in a plan view, the active region includes a first portion (e.g. region of 14) and a second portion (e.g. region of 18) narrower than the first portion;
forming a first gate stack (11, see [0014]) for the first active region; and
forming a second gate stack (58, see [0019]) for the second active region.
Bentum does not disclose
forming a first active region in which first semiconductor layers and second semiconductor layers are alternatingly stacked over a first lower fin element;
removing the first semiconductor layers of the first active region, wherein the second semiconductor layers of the first portion of the first active region form a plurality of first nanostructures, and the second semiconductor layers of the second portion of the first active region form a plurality of second nanostructures;
forming a first gate stack to surround the plurality of first nanostructures; and
forming a second gate stack to surround the plurality of second nanostructures.
In the same field of endeavor, Liaw teaches in Fig. 2A-9D and related text a method making a semiconductor device comprising
forming a first active region (e.g. region of first and second nanostructures, see annotated Fig. 2B below) in which first semiconductor layers and second semiconductor layers (210A/210B, see [0020]) are alternatingly stacked over a first lower fin element (202N/202N-T, see Figs. 3A-D);
removing the first semiconductor layers of the first active region (see Fig. 7A), wherein the second semiconductor layers of the first portion of the first active region form a plurality of first nanostructures (210A), and the second semiconductor layers of the second portion of the first active region form a plurality of second nanostructures (210A);
forming a first gate stack (240/242/244 over first nanostructures, see [0036] and [0044]) to surround the plurality of first nanostructures; and
forming a second gate stack (240/242/244 over second nanostructures, see [0036] and [0044]) to surround the plurality of second nanostructures.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Bentum by forming a first active region in which first semiconductor layers and second semiconductor layers are alternatingly stacked over a first lower fin element, removing the first semiconductor layers of the first active region, wherein the second semiconductor layers of the first portion of the first active region form a plurality of first nanostructures, and the second semiconductor layers of the second portion of the first active region form a plurality of second nanostructures, forming a first gate stack to surround the plurality of first nanostructures, and forming a second gate stack to surround the plurality of second nanostructures, as taught by Liaw, in order to provide a method of making a nanosheet device which provides aggressive scaling down of device size (see Liaw [0001]).
Regarding claim 2, the combined device shows wherein the first gate stack surrounds the plurality of first nanostructures to form a pull-down transistor of a static random access memory cell, and the first gate stack surrounds the plurality of second nanostructures to form a pass-gate transistor of the static random access memory cell (Bentum: see [0014]); Liaw: see Figs. 2A-B and [0016]).
Regarding claim 3, the combined device shows
forming a second active region (Liaw: e.g. region of third and fourth nanostructures, see annotated Fig. 2B above) in which the first semiconductor layers and the second semiconductor layers (210B/21A) are alternatingly stacked over a second lower fin element (202P/202P-T, see Figs. 3A-D);
removing the first semiconductor layers of the second active region (Liaw: see Fig. 7A) to form a plurality of third nanostructures (210A) and a plurality of fourth nanostructures (210A);
forming the first gate stack (240/242/244 over first nanostructures) to surround the plurality of third nanostructures (see Fig. 2B); and
forming the second gate stack (240/242/244 over second nanostructures) to surround the plurality of second nanostructures (see Fig. 2B),
wherein a first distance between the plurality of first nanostructures and the plurality of third nanostructures (Bentum: distance between active region at 14 and active region at 10) is substantially equal to a second distance between the plurality of second nanostructures and the plurality of fourth nanostructures (distance between active region at 18 and active region at 22, see Fig. 2).
Regarding claim 4, the combined device shows the first portion of the first active region has a first sidewall extending in a first horizontal direction, the second portion of the first active region has a second sidewall extending in the first horizontal direction, and the first sidewall is connected to the second sidewall through a connecting wall (Bentum: first portion at 14, second portion at 18, see Fig. 2).
Regarding claim 7, the combined device further shows the connecting wall overlaps the first gate stack or the second gate stack (e.g. in a cross sectional view).
Regarding claim 8, the combined device shows further comprising: forming a source/drain feature (Liaw: 230, see [0028]) on the first lower fin element to adjoin both the plurality of first nanostructures and the plurality of second nanostructures.
Regarding claim 9, the combined device shows patterning the first lower fin element to form an opening exposing a bottom of the source/drain feature (Liaw: see Figs. 8D and 9D, inverted); and
forming a contact plug (260) in the opening.
Regarding claim 10, Bentum and Liaw substantially teach the claimed invention in the same manner and for the same reasons as applied to claims 1 and 3 above.
Bentum and Liaw further teach patterning the sacrificial layers, the channel layers and the substrate to form a first fin structure in a p-type well of the substrate and a second fin structure in an n-type well of the substrate (Liaw: see [0018]); and
forming a dummy gate structure (Bentum: 11; Liaw: 220, see [0023] in position of final gate structure 240/242/244 over first nanostructures and third nanostructures) across the first fin structure and the second fin structure, wherein the dummy gate structure overlaps the first protruding portion of the first fin structure (Bentum: see Fig. 2).
Regarding claim 11, the combined device wherein the protruding portion of the first fin structure extends a distance toward the second fin structure in a first direction that is parallel to a longitudinal axis of the first dummy gate structure (Bentum: see Fig. 2).
Regarding claim 12, the combined device shows wherein the strip portion of the first fin structure has a first dimension in the first direction, and the second fin structure has a second dimension in the first direction, and the second dimension is substantially equal to the first dimension (Bentum: see Fig. 2).
Regarding claim 13, the combined device shows wherein the sacrificial layers, the channel layers and the substrate are patterned to form a third fin structure in the p-type well of the substrate, and the first fin structure includes a second protruding portion extending toward the third fin structure (see repeating structure of Bentum, Fig. 2).
Regarding claim 14, the combined device shows wherein patterning the sacrificial layers, the channel layers and the substrate comprises:
etching the sacrificial layers, the channel layers and the substrate in a first etching process to form a first semiconductor strip and a second semiconductor strip (Liaw: see [0021]); and
etching the first semiconductor strip and the second semiconductor strip in a second etching process after the first etching process, wherein the first semiconductor strip is partially cut to form the first fin structure, and the second semiconductor strip is partially removed to form the second fin structure (Liaw: see [0022]).
Regarding claim 15, the combined device shows
removing the dummy gate structure (Liaw: see Figs. 6A-C and [0031]);
removing the sacrificial layers (Liaw: see [0034]-[0035]) of the first fin structure and the second fin structure; and
forming a gate stack (240/242/244 over first nanostructures, see [0036] and [0044]) surrounding the channel layers the first fin structure and the second fin structure.
Regarding claim 21, Bentum and Liaw substantially teach the claimed invention in the same manner and for the same reasons as applied to claims 1 and 10 above.
Regarding claim 22, the combined device shows wherein the etching provides the first portion having a first sidewall extending in a first horizontal direction, the second portion having a second sidewall extending in the first direction, wherein the first sidewall and the second sidewall are connected through a connecting wall (Bentum: first portion at 14, second portion at 18, see Fig. 2).
Regarding claim 24, the combined device shows
interconnecting a source/drain terminal associated with the first gate stack with a source/drain terminal associated with the second gate stack (Liaw: see Fig. 9B);
using the first gate stack to provide a pull-down transistor and using the second gate stack provides a pass-gate transistor (Bentum: see [0014]); Liaw: see Figs. 2A-B and [0016]).
Claim(s) 6, 23 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bentum in view of Liaw, as applied to claims 1 and 21 above, and in view of Ong et al. (US 20230209797; herein “Ong”).
Regarding claim 6, Bentum does not disclose wherein the connecting wall is curved or a straight line that extends in a direction inclined to the first horizontal direction.
In the same field of endeavor, Ong teaches in Fig. 2B-D and related text a semiconductor device wherein the connecting wall (e.g. 205/210/215, see [0037]) is curved or a straight line that extends in a direction inclined to the first horizontal direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Bentum by having the connecting wall be curved or a straight line that extends in a direction inclined to the first horizontal direction, as taught by Ong, in order to employ another well-known resulting shape of the patterning process and because it has little effect on the performance of the device (see Ong [0034] and [0037]). Additionally, such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04
Regarding claim 23, Ong further teaches the limitation in the same manner and for the same reasons as applied to claim 6 above.
Regarding claim 25, the combined device shows epitaxially growing a source/drain feature to form the source/drain terminal of the first pull-down transistor and the pass-gate transistor share a source/drain feature (Liaw: 230, see [0028]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896
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