DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II in the reply filed on 3/24/2026 is acknowledged.
Information Disclosure Statement
Acknowledgement is made of Applicant's Information Disclosure Statement (IDS) from PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-22, 27 and 29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karino et al. (US 2023/0378245 A1).
Re Claim 21, Karino teaches a method, comprising:
forming a thin film resistor (TFR) with a taper profile (3b, Fig. 20, para [0113]);
forming a first contact (3c + 9, Fig. 20, paras [0062] and [0113]) physically contacting a first portion of the TFR (3b, see Fig. 20); and
forming a second contact (3a + 13, Fig. 20, paras [0113] - [0114]) physically contacting a second portion of the TFR (3b, see Fig. 20).
Re Claim 22, Karino teaches the method of claim 21, further comprising: forming a first dielectric layer (insulating layer 4, Fig. 20) contacting a first side of the TFR (bottom side of 3b, Fig. 20); and forming a second dielectric layer (insulating layer 5, Fig. 20) physically contacting a second side (top side of 3b, Fig. 20), opposite the first side, of the TFR.
Re Claim 27, Karino teaches the method of claim 21, further comprising: forming a first metal plug (metal contact 8, Fig. 20) physically contacting the first contact (3c + 9); and forming a second metal plug (metal contact 12, Fig. 20) physically contacting the second contact (3a + 13).
Re Claim 29, Karino teaches the method of claim 21, wherein the TFR (3b, Fig. 20) is included in an interconnect region of a semiconductor device (see Fig. 20).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17, 19-20, 23-26 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Karino et al. (US 2023/0378245 A1).
Re Claim 17, Karino teaches a method, comprising:
patterning a semiconductor stack into a taper profile (4+3a+3b+3c+5, Fig. 20, para [0113], also see Figs. 7-10 on how the layers are formed, paras [0080] – [0092]), wherein the semiconductor stack includes a first dielectric layer (insulating layer 4, Fig. 20), a thin film resistor (TFR) (3a+3b+3c, Fig. 20), and a second dielectric layer (insulating layer 5, Fig. 20) and is over a supporting dielectric layer (insulating layer 2, Fig. 20);
forming an oxide layer (insulating layer 6, Fig. 20, see Examiner comments below) over the second dielectric layer (insulating layer 2, Fig. 20);
forming a first contact (contact 9, Fig. 20, paras [0062] and [0113]) and a second contact (contact 13, Fig. 20, paras [0113] - [0114]), within the oxide layer (insulating layer 6, Fig. 20), that physically contact the TFR (3a+3b+3c, Fig. 20);
forming an inter-metal dielectric (IMD) layer (passivation film 7, Fig. 20) over the oxide layer (insulating layer 6, Fig. 20); and
forming, within the IMD layer (passivation film 7, Fig. 20), a first metal plug (metal contact 8, Fig. 20) that physically contacts the first contact (contact 9, Fig. 20) and a second metal plug (metal contact 12, Fig. 20) that physically contacts the second contact (contact 13, Fig. 20).
Regarding the oxide layer, Karino does not explicitly disclose that the insulating layer 6 is an oxide layer in the embodiment of Fig. 20. However, it is similar to the insulating layer 5 in the embodiment of Fig. 2 which can be made of silicon oxide (compare paras [0060] and [0052]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to form the insulating layer 6 in the device of Fig. 20 from silicon oxide as it has been disclosed by Karino in earlier embodiments.
Re Claim 19, Karino teaches the method of claim 17, wherein the TFR (3a+3b+3c, Fig. 20) includes a first end portion (31, Fig. 16B) and a second end portion (33, Fig. 16B) that are wider than a middle portion (35, Fig. 16B), the first contact (contact 9, Fig. 20) has a bottom surface with a smaller surface area than the first end portion of the TFR (bottom surface of contact 9 is smaller than the area of end portion, see Fig. 21), and the second contact (contact 13, Fig. 20) has a bottom surface with a smaller surface area than the second end portion of the TFR (contact 13 is similar to contact 9, and hence bottom surface of contact 13 is smaller than the area of end portion, see Fig. 21).
Re Claim 20, Karino teaches the method of claim 17, but does not explicitly disclose that the IMD layer (passivation film 7, Fig. 20) is substantially free of voids.
However, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the IMD layer of Karino has to be substantially free of voids, otherwise it can cause current-leakage, and will not be a functional device.
Re Claim 23, Karino teaches the method of claim 22, but does not explicitly disclose that the first dielectric layer (insulating layer 4, Fig. 20) and the second dielectric layer (insulating layer 5, Fig. 20) comprise undoped silicate glass.
However, in an earlier embodiment, Karino discloses that the insulating layers can be made of silicon oxide (para [0052]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to form the insulating layers in the device of Fig. 20 from silicon oxide as it has been disclosed by Karino in earlier embodiments.
Re Claim 24, Karino teaches the method of claim 22, further comprising: forming a layer (insulating layer 6, Fig. 20) over the second dielectric layer (insulating layer 5, Fig. 20) and surrounding the first contact (3c + 9) and the second contact (3a + 13).
Karino does not explicitly disclose that the insulating layer 6 is an oxide layer in the embodiment of Fig. 20. However, it is similar to the insulating layer 5 in the embodiment of Fig. 2 which can be made of silicon oxide (compare paras [0060] and [0052]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to form the insulating layer 6 in the device of Fig. 20 from silicon oxide as it has been disclosed by Karino in earlier embodiments.
Re Claim 25, Karino teaches the method of claim 24, further comprising: forming an inter-metal dielectric (IMD) layer (passivation film 7, Fig. 20) over the oxide layer (insulating layer 6, Fig. 20).
Re Claim 26, Karino teaches the method of claim 25, but does not explicitly disclose that the IMD layer (passivation film 7, Fig. 20) is substantially free of voids.
However, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the IMD layer of Karino has to be substantially free of voids, otherwise it can cause current-leakage, and will not be a functional device.
Re Claim 28, Karino teaches the method of claim 21, wherein sidewalls of the TFR (sidewalls of 3b, Fig. 20) form one or more angles with a horizontal axis but does not disclose that the angles are in a range from approximately 70 degrees to approximately 80 degrees.
Karino shows that the tapered sidewalls of the TFR (sidewalls of 3b, Fig. 20) have an angle of approximately 45 degrees with the horizontal. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the tapered angle of the sidewalls of the TFR, depending on the thickness of the TFR and the surrounding dielectric layers and arrive at the claimed range. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed angle range would have been obvious to one of ordinary skill in the art.
Allowable Subject Matter
Claims 10-16 are allowed.
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10 is allowable at least for the following reasons. Karino et al. (US 2023/0378245 A1) teaches most of the limitations of claim 1 as follows: forming a first photoresist layer (see para [0085], where a mask is formed over layer 4 to pattern it, the mask is not shown) over a semiconductor stack (2+3a+4, Fig. 20) including a first dielectric layer (insulation layer 2), a thin film resistor (TFR) (resistor 3a), and a second dielectric layer (insulation layer 4); patterning the semiconductor stack into a taper profile (tapering the layer 4) using the first photoresist layer (para [0085], Fig. 10); forming an oxide layer (insulation layer 6, Fig. 20) over the second dielectric layer (insulation layer 4); forming a second photoresist layer over the oxide layer (mask layer, not shown, formed above insulation layer 6 to form the recess, para [0089]); forming a first recess (recess for contact 9) and a second recess (recess for contact 13) in the oxide layer using the second photoresist layer; expanding the first recess and the second recess to expose a portion of the TFR (see Fig. 20); forming a first contact in the first recess and a second contact in the second recess (see Fig. 20); forming an inter-metal dielectric (IMD) layer (passivation layer 7, Fig. 20) over the oxide layer. Karino fails to teach, “forming a third recess and a fourth recess in the IMD layer; and forming a first metal plug in the third recess and a second metal plug in the fourth recess.”
Related art, Hsu et al. (US 2023/0063793 A1) also teaches most of the limitations of claim 10 as follows: forming a first photoresist layer (mask layer, not shown, to pattern the structure of Fig. 5A, para [0063]) over a semiconductor stack (110+112+114+302, Fig. 4) including a first dielectric layer (110), a thin film resistor (TFR) (resistor 112+114), and a second dielectric layer (302); patterning the semiconductor stack using the first photoresist layer (para [0063], Figs. 6A-8A); forming an oxide layer (118, Figs. 4 and 10A) over the second dielectric layer (302); forming a second photoresist layer over the oxide layer (similar mask will be formed over 118 to form the recesses for contacts 120, Fig. 4, para [0025]); forming a first recess and a second recess in the oxide layer using the second photoresist layer (recesses for contacts 120, Fig. 4, para [0025]); expanding the first recess and the second recess to expose a portion of the TFR (112+114, Fig. 4); forming a first contact in the first recess and a second contact in the second recess (contacts 120, Fig. 4); forming an inter-metal dielectric (IMD) layer (IMD layer 416, Fig. 4, para [0051]) over the oxide layer (118); forming a third recess and a fourth recess in the IMD layer (recesses for contacts 106, Fig. 4, para [0054]); and forming a first metal plug in the third recess and a second metal plug in the fourth recess (contacts 106, Fig. 4, para [0054]). Hsu does not teach a tapered semiconductor stack. Related art, Eshun et al. (US 2005/0258513 A1) teaches a tapered semiconductor stack including a TFR (35+50+55) as shown in Figs. (1-4B). However, in the Examiner’s opinion, it would not be obvious to one of ordinary skill to combine the above the teachings to reach the full limitation of claim 10.
Claim 11-16 depend from claim 10 are allowable for at least the reasons above.
Claim 18 is allowable at least for the reasons of, “a first portion of a top surface of the oxide layer, over the semiconductor stack, is farther from a top surface of the supporting dielectric layer than a second portion of the top surface of the oxide layer, adjacent to the semiconductor stack”. Karino et al. (US 2023/0378245 A1) teaches the oxide layer (insulating layer 6, Fig. 20) and the supporting dielectric layer (insulating layer 2, Fig. 20) as stated in the rejection of the independent claim 17 above. The insulating layer 6 has a flat top surface and hence the distance from the top surface of the insulating layer 6 to the top surface of the supporting dielectric layer 20 will always be constant and thus does not teach the limitation of claim 18. Thus, the limitation is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion, when viewed in the context of the independent claim 17, as a whole.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dirnecker et al. (US 2014/0239449 A1) shows a similar tapered thin-film resistor in Figs. 4D/4E.
Lee et al. (US 2013/0093055 A1) also shows a similar tapered thin-film resistor in Fig. 3.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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