Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15, 19, 20, 21 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 11355605) in view of Yu et al (US 20210408249).
Regarding claims 15 and 21, Lee et al teaches
[claim 15] A method, comprising: forming a stack of nanostructures over a substrate (figures 3A and 6A, col 7 lines 42-59, where the nanostructures is element 120 situated above the red line as shown in figure 1 below is defined as “the stack of nanostructures.” It can also be noted that figure 6A shows the part of element 120 not part of the nanostructures);
forming a source/drain opening to a first level below the stack of nanostructures (figures 3A and 6A, col 8 lines 1-13, where element 184 is the source/drain opening formed at a first level below the nanostructure, where the bottom level of element 184 extends below the defined nanostructure as shown in figure 1 below);
forming an extended source/drain opening by extending the source/drain opening to a second level below the first level (figures 3A and 6A, col 8 liens 1-13, where element 182 is the source/drain extension to a second level below the nanostructures [element 120]);
forming a first material layer in the extended source/drain opening (figure 3A, col 8 lines 41-46, where element 180 [comprising element 184 and 182] is made of a first material layer in element 182); and
[claim 21] forming a stack of semiconductor channels over a substrate (figures 3A and 6A, col 7 lines 42-59, where the nanostructures is element 120 situated above the red line as shown in figure 1 below is defined as “the stack of nanostructures.” It can also be noted that figure 6A shows the part of element 120 not part of the nanostructures);
forming a source/drain trench adjacent to the channels and extending into the substrate (figures 3A and 6A, col 8 lines 1-13, where element 184 is the source/drain opening formed into the substrate [element 50], where the bottom level of element 184 extends below the defined nanostructure as shown in figure 1 below);
depositing a first semiconductor layer of a hybrid structure in the source/drain trench (figure 3A, col 8 lines 41-46, where element 180 [comprising element 184 and 182] is made of a first material layer in element 182);
and depositing a gate structure wrapping around the semiconductor channels (figure 1C, col 5 lines 39-45 where element 150a is the gate and wraps around the semiconductor channel [stacks situated over element 114]).
However, Lee et al does not specifically disclose
[claim 15] forming a semiconductor feature in the extended source/drain opening adjacent the first material layer; forming an isolation structure including forming an isolation opening in the first material layer; and forming a source/drain region on the semiconductor feature and on respective sidewalls of the stack of nanostructures; and
[claim 21] depositing an isolation region of the hybrid structure extending vertically from an upper surface of the first semiconductor layer to a level above a bottom surface of the first semiconductor layer; and depositing a source/drain region in the source/drain trench over the hybrid structure.
However, Yu et al does teach
[claim 15] forming a semiconductor feature in the extended source/drain opening adjacent the first material layer (figure 12C, paragraph 0045, where element 91 is the semiconductor feature [epitaxial layer] formed in the extended source/drain opening [as noted in figure 12 C there is an extension beyond the normal source drain as presented under element 92 on the right-hand side);
forming an isolation structure including forming an isolation opening in the first material layer (figure 12C, paragraph 0045, where element 89 is the isolation structure formed in the first material layer situated in the region over the extended source/drain region as characterized by the region where element 91 is formed. Additionally an isolation opening [as noted by the curvature of element 89] is formed with the interpretation of “opening” being similar to “an opening in the rocks” which means an indent, or a cave-like feature);
and forming a source/drain region on the semiconductor feature and on respective sidewalls of the stack of nanostructures (figure 12C, paragraph 0045, where elements 92A and 92B comprise the source/drain semiconductor features formed on the sidewalls of the nanostructures [elements 54A and B]).
[claim 21] depositing an isolation region of the hybrid structure extending vertically from an upper surface of the first semiconductor layer to a level above a bottom surface of the first semiconductor layer (figure 12C, paragraph 0045, where element 89 is the isolation region of the structure [layer deposited within the source/drain trenches] which extends vertically from an upper surface of the first semiconductor layer [element 91] to a level above said first layer [by nature if it extends from the top of the surface it will be above the bottom portion of the surface]);
depositing a source/drain region in the source/drain trench over the hybrid structure (figure 12C, paragraph 0045, where elements 92A and 92B comprise the source/drain semiconductor features formed on the sidewalls of the nanostructures [elements 54A and B]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee et al to incorporate the teachings of Yu et al in order to guard the source/drain region from any adverse effects of formation of backside material of the finFet transistor device, as it is known when forming through vias or other backside features the source/drain recesses in the substrate can be significantly affected.
Regarding claims 19, 20 and 23,
Lee et al teaches all of the limitations of the parent claim, claim 15, but does not specifically disclose
[claim 19] The method of claim 15, wherein the forming a semiconductor feature includes forming the semiconductor feature that is in direct contact with the substrate.
[claim 20] The method of claim 15, wherein the forming a semiconductor feature includes forming the semiconductor feature extending to a third level between the first level and the second level, the first material layer being vertically between the semiconductor feature and the substrate.
[claim 23] The method of claim 21, wherein the isolation region includes a void.
However, Yu et al further discloses
[claim 19] The method of claim 15, wherein the forming a semiconductor feature includes forming the semiconductor feature that is in direct contact with the substrate (figure 12C, paragraph 0045, where elements 91 and 89 comprise the semiconductor feature and are in direct contact with the substrate [element 50]).
[claim 20] The method of claim 15, wherein the forming a semiconductor feature includes forming the semiconductor feature extending to a third level between the first level and the second level, the first material layer being vertically between the semiconductor feature and the substrate (figure 12C, paragraph 0045, where elements 89 and 91 comprise the semiconductor feature and extends to a third level situated between the first [bottom portion of the source/drain recess] and the second level [top portion of element 89], where said third level is the interface between elements 89 and 91 and the semiconductor feature extends vertically within said third level).
[claim 23] The method of claim 21, wherein the isolation region includes a void (figure 12C, paragraph 0045, where element 91 is the isolation region with an “opening” or “inlet” defined by the concave structure of the layer, similar to an “opening in a rock” where the “opening” or “void” is just an inlet in the rock).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee et al to incorporate the teachings of Yu et al in order to guard the source/drain region from any adverse effects of formation of backside material of the finFet transistor device, as it is known when forming through vias or other backside features the source/drain recesses in the substrate can be significantly affected.
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Figure 1: From Figure 3A of Lee et al
Claim(s) 16-18, 22, 24 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 11355605) and Yu et al (US 20210408249) and in further view of Lin et al (US 20220052181).
Lee et al teaches all of the limitations of the parent claims, claims 15 and 21, but does not specifically disclose
[claim 16] The method of claim 15, wherein the forming an isolation structure includes: forming a dielectric layer in the isolation opening.
[claim 17] The method of claim 16, wherein the forming a dielectric layer includes forming the dielectric layer having a seam therein.
[claim 18] The method of claim 16, wherein the forming a dielectric layer includes forming the dielectric layer that partially fills the isolation opening.
[claim 22] The method of claim 21, wherein the isolation region includes a dielectric material.
[claim 24] The method of claim 23, wherein the isolation region includes a dielectric material and the void is a seam in the dielectric material.
[claim 27] The method of claim 21, further comprising: a bottom insulator between the source/drain region and the hybrid structure.
However, Lin et al does teach
[claim 16] The method of claim 15, wherein the forming an isolation structure includes: forming a dielectric layer in the isolation opening (figure 9, paragraph 0033, where element 57 is the dielectric layer formed in an isolation opening, where the isolation opening is in the same location as the opening of element 55 below element 57, where element 55 fills in said opening).
[claim 17] The method of claim 16, wherein the forming a dielectric layer includes forming the dielectric layer having a seam therein (figure 9, paragraph 0033, where element 57 has a seam that extends up the sidewalls of the nanostructures [element 52/54 stack]).
[claim 18] The method of claim 16, wherein the forming a dielectric layer includes forming the dielectric layer that partially fills the isolation opening (figure 9, paragraph 0033, where element 57 is the dielectric layer formed in an isolation opening, where the isolation opening is in the same location as the opening of element 55 below element 57, where element 55 fills in said opening, and it fill part of the isolation opening).
[claim 22] The method of claim 21, wherein the isolation region includes a dielectric material (figure 9, paragraph 0033, where element 57 is the dielectric layer formed in an isolation opening, where the isolation opening is in the same location as the opening of element 55 below element 57, where element 55 fills in said opening).
[claim 24] The method of claim 23, wherein the isolation region includes a dielectric material and the void is a seam in the dielectric material (figure 9, paragraph 0033, where element 57 has a seam that is the bottom portion of the dielectric material that fills in the void of the isolation region – where the void is defined as the “opening” of the structure of Yu et al from Lee et al as modified just as an inlet of a rock is an “opening” of a rock, so too is the concave portion [inlet, opening, void] of the structure of Lee et as as modified).
[claim 27] The method of claim 21, further comprising: a bottom insulator between the source/drain region and the hybrid structure (figure 9, paragraph 0033, where element 57 is the bottom insulator between the source/drain region [section above element 57] and the hybrid structure [element 55 read onto from Lee et al as modified, where the structure of Lee et al as modified is in the location of element 55 of Lin et al]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee et al to incorporate the teachings of Lin et al in order to use a dielectric material in the source/drain recess to provide adequate electrical isolation from the channel regions to maximize performance of the transistor and utilize the electric field effect to induce current in the channel layer.
Allowable Subject Matter
Claim 28 is allowed. In particular, claim 28 specifies the formation of two nanostructures, both having an extended source/drain region formed. In particular the language of “the first hybrid structure including a first semiconductor feature and a first isolation region between the first semiconductor feature and the substrate, depositing a first source/drain region of the first transistor in the first source/drain trench adjacent the first stack of nanostructures and over the first hybrid structure; depositing a second hybrid structure in a second source/drain trench extending into the substrate, the second hybrid structure including a second semiconductor feature and a second isolation region between the second semiconductor feature and the substrate,” in combination with the other limitations of claim 28 read over the prior art. The closest prior art Lin et al (US 20220052181) communicates two different layers in a source/drain region as seen in figure 9, paragraph 0033. Elements 55 and 57 comprise two separate structures within each source/drain region but they do not contain hybrid structures including semiconductor features as well as isolation regions between said semiconductor feature and the substrate. Element 55 and 57 are both dielectric spacers for the channel regions [element 52]. Additionally, Yu et al (US 20210408249) specifies two separate types of structures within an extended source/drain region in figure 12C, paragraphs 0045-0050, where elements 91 and 89 are two elements within the extended source/drain region but do not comprise a semiconductor region with an isolation region situated between the semiconductor region and the substrate. Additionally, there is only one shown situated between two nanostructures, rather than two shown with the two nanostructures. Lastly, Lu et al (US 20220359679) is similar to Yu et al, figure 18A shows elements 100 and 102 as two unique layer deposited in an extended source/drain region. Sam as Yu et al, the form of the two are not a semiconductor and isolation region where the isolation region is between the substrate and semiconductor region. Additionally, there is only one shown with three nanostructure stacks. It would not have been obvious to read different material into these specific situations for the purpose of forming the source/drain as other prior art would require the materials to be formed within a specific location, not just generically formed on a transistor. No other prior art was found where the specific formation of a semiconductor layer and an isolation layer where the isolation layer is situated between the semiconductor layer and the substrate with two separate nanostructure stacks was found, thus claim 28 reads over the prior art and is in a state of allowance.
Subsequently, claims 29-34 are also in a state of allowance because they depend upon an allowable claim and thus further limit the limitations of allowable claim 28.
Claims 25 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lin et al (US 20230271045), Chen et al (US 20230063463), Huang et al (US 20220359375), and Lu et al (US 20220359679) as similar finFET devices, and formation therein, where different materials are formed within source/drain recesses.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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