Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tatsuo (US20240096938A1) and Landis(US20170363954A1).
With respect to Claim 1 Tatsuo teaches in Fig 5 and Fig 6, a method, comprising:
providing a device structure including an epitaxial layer (Fig 5; 24; ¶ [0108]) and a hard mask (Fig 5; 40; ¶ [0109]) over the epitaxial layer;
forming a set of trenches through the epitaxial layer (Fig 5; 24; ¶ [0108]), wherein each trench of the set of trenches is defined by a sidewall and a bottom surface (Fig 6; 11; ¶ [0111]);
forming an ashable mask over the device structure including within each trench of the set of trenches (Fig 10; 46; ¶ [0131]); and
forming an implanted region in the epitaxial layer (Fig 5; 24; ¶ [0108]), below the bottom surface of each trench (Fig 8; 32; ¶ [0142]).
Tatsuo does not teach by delivering ions into the set of trenches while the ashable mask is along the sidewall and the bottom surface of each trench of the set of trenches.
Landis teaches by delivering ions (Fig 5c; 421; ¶ [0098]) into the set of trenches while the ashable mask (Fig 5b; 115; ¶ [0150]) is along the sidewall and the bottom surface of each trench of the set of trenches.
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Tatsuo, a semiconductor device with epitaxial layers with trenches and implantation regions beneath the trenches, and the invention of Landis, a semiconductor device with that uses an ashable (carbon) layer to protect the trenches during the ion implantation. This combination produces a semiconductor device with epitaxial layers with trenches protected by an ashable (carbon) layer during the ion implantation to form an implanted region in the epitaxial layer. The ashable layer protects the pattern during the ion implantation and is advantageously a carbon layer Landis(¶ [0150).
With respect to Claim 2, Tatsuo and Landis teach the method of claim 1.
Tatsuo teaches in Fig 10, wherein forming the ashable mask comprises depositing a carbon ashable hard mask along the sidewall and the bottom surface (Fig 10; 46; ¶ [0131]).
With respect to Claim 3, Tatsuo and Landis teach the method of claim 2.
Tatsuo teaches in Fig 10, wherein a first thickness of the carbon ashable hard mask along the sidewall is different than a second thickness of the carbon ashable hard mask along the bottom surface(Fig 10; 46; ¶ [0131]).
With respect to Claim 4, Tatsuo and Landis teach the method of claim 1.
Tatsuo teaches in Fig 11, wherein each trench of the set of trenches has a first width (Fig 11; 11; ¶ [0135]), wherein the implanted region has a second width (Fig 11; 32y; ¶ [0142]), and wherein the second width is less than the first width.
With respect to Claim 5, Tatsuo and Landis teach the method of claim 1.
Tatsuo teaches wherein delivering ions into the set of trenches comprises performing a vertical ion implant (Fig 9; ion implantation Al; ¶ [0125]).
With respect to Claim 6, Tatsuo and Landis teach the method of claim 1.
Tatsuo teaches in Fig 6, wherein providing the device structure further comprises forming a source region (Fig 6; 26; ¶ [0077]) over a well, wherein the trench (Fig 6; 11; ¶ [0076]) is formed through the epitaxial layer (Fig 6; 24; ¶ [0077]), the well (Fig 6; 26; ¶ [0077]), and the source region (Fig 6; 28; ¶ [0077]).
With respect to Claim 7, Tatsuo and Landis teach the method of claim 1.
Tatsuo teaches wherein the implanted region is an n-type implanted region or a p-type implanted region (Fig 9; 32y; ¶ [0037]; p type).
With respect to Claim 8, Tatsuo teaches a method of forming a transistor, comprising:
providing a device structure including an epitaxial layer (Fig 5; 24; ¶ [0108]) and a hard mask (Fig 5; 40; ¶ [0109]) over the epitaxial layer;
forming a set of trenches through the epitaxial layer (Fig 5; 24; ¶ [0108]), wherein each trench of the set of trenches is defined by a sidewall and a bottom surface extending from the sidewall (Fig 6; 11; ¶ [0111]);
forming an ashable mask over the device structure including along the sidewall and the bottom surface of each trench of the set of trenches (Fig 10; 46; ¶ [0131]); and
forming an implanted region in the epitaxial layer (Fig 5; 24; ¶ [0108]), below the bottom surface of each trench (Fig 8; 32; ¶ [0142]).
Tatsuo does not teach by delivering ions into the set of trenches and through the ashable mask.
Landis teaches by delivering ions (Fig 5c; 421; ¶ [0098]) into the set of trenches and through the ashable mask (Fig 5b; 115; ¶ [0150]).
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Tatsuo, a semiconductor device with epitaxial layers with trenches and implantation regions beneath the trenches, and the invention of Landis, a semiconductor device with that uses an ashable (carbon) layer to protect the trenches during the ion implantation. This combination produces a semiconductor device with epitaxial layers with epitaxial trenches protected by an ashable (carbon) layer during the ion implantation to form an implanted region in the epitaxial layer. The ashable layer protects the pattern during the ion implantation and is advantageously a carbon layer Landis(¶ [0150) .
With respect to Claim 9, Tatsuo and Landis teach the method of claim 8.
Tatsuo teaches in Fig 10, wherein forming the ashable mask comprises depositing a carbon ashable hard mask along the sidewall and the bottom surface (Fig 10; 46; ¶ [0131]).
With respect to Claim 10, Tatsuo and Landis teach the method of claim 9.
Tatsuo teaches in Fig 10, wherein a first thickness of the carbon ashable hard mask along the sidewall is different than a second thickness of the carbon ashable hard mask along the bottom surface(Fig 10; 46; ¶ [0131]).
With respect to Claim 11, Tatsuo and Landis teach the method of claim 8.
Tatsuo teaches in Fig 11, wherein each trench of the set of trenches has a first width (Fig 11; 11; ¶ [0135]), wherein the implanted region has a second width (Fig 11; 32y; ¶ [0142]), and wherein the second width is less than the first width.
With respect to Claim 12, Tatsuo and Landis teach the method of claim 8.
Tatsuo teaches wherein delivering ions into the set of trenches comprises performing a vertical ion implant (Fig 9; ion implantation Al; ¶ [0125]).
With respect to Claim 13, Tatsuo and Landis teach the method of claim 8.
Tatsuo teaches in Fig 6, wherein providing the device structure further comprises forming a source region (Fig 6; 26; ¶ [0077]) over a well, wherein the trench (Fig 6; 11; ¶ [0076]) is formed through the epitaxial layer (Fig 6; 24; ¶ [0077]), the well (Fig 6; 26; ¶ [0077]), and the source region (Fig 6; 28; ¶ [0077]).
With respect to Claim 14, Tatsuo and Landis teach the method of claim 8.
Tatsuo teaches wherein the implanted region is an n-type implanted region or a p-type implanted region (Fig 9; 32y; ¶ [0037]; p type).
With respect to Claim 15, Tatsuo teaches in Fig 5 and Fig 6 a method of forming a silicon carbide metal-oxide-semiconductor field-effect transistor, the method comprising:
providing a device structure including an epitaxial layer (Fig 5; 24; ¶ [0108]) and a hard mask (Fig 5; 40; ¶ [0109 over the epitaxial layer;
forming a set of trenches through the epitaxial layer (Fig 5; 24; ¶ [0108]), wherein each trench of the set of trenches is defined by a sidewall and a bottom surface extending from the sidewall (Fig 6; 11; ¶ [0111]);
forming an ashable mask over the device structure including along the sidewall and the bottom surface of each trench of the set of trenches (Fig 10; 46; ¶ [0131]); and
forming an implanted region in the epitaxial layer(Fig 5; 24; ¶ [0108]), below the bottom surface of each trench (Fig 8; 32; ¶ [0142]).
Tatsuo does not teach by delivering ions through the ashable mask along the bottom surface of each trench of the set of trenches.
Landis teaches by delivering ions (Fig 5c; 421; ¶ [0098]) through the ashable mask (Fig 5b; 115; ¶ [0150]) along the bottom surface of each trench of the set of trenches.
It is obvious to one with ordinary skill in the art before the effective filing date of the invention to combine the invention of Tatsuo, a semiconductor device with epitaxial layers with trenches and implantation regions beneath the trenches, and the invention of Landis, a semiconductor device with that uses an ashable (carbon) layer to protect the trenches during the ion implantation. This combination produces a semiconductor device with epitaxial layers with trenches protected by an ashable (carbon) layer during the ion implantation to form an implanted region in the epitaxial layer. The ashable layer protects the pattern during the ion implantation and is advantageously a carbon layer Landis(¶ [0150).
With respect to Claim 16, Tatsuo and Landis teach the method of claim 15.
Tatsuo teaches in Fig 10, wherein forming the ashable mask comprises depositing a carbon ashable hard mask along the sidewall and the bottom surface (Fig 10; 46; ¶ [0131]).
With respect to Claim 17, Tatsuo and Landis teach the method of claim 16.
Tatsuo teaches in Fig 10, wherein a first thickness of the carbon ashable hard mask along the sidewall is different than a second thickness of the carbon ashable hard mask along the bottom surface (Fig 10; 46; ¶ [0131]).
With respect to Claim 18, Tatsuo and Landis teach the method of claim 15.
Tatsuo teaches in Fig 11, wherein each trench of the set of trenches has a first width (Fig 11; 11; ¶ [0135]), wherein the implanted region has a second width (Fig 11; 32y; ¶ [0142]), and wherein the second width is less than the first width.
With respect to Claim 19, Tatsuo and Landis teach the method of claim 15.
Tatsuo teaches wherein delivering ions into the set of trenches comprises performing a vertical ion implant (Fig 9; ion implantation Al; ¶ [0125]).
With respect to Claim 20, Tatsuo and Landis teach the method of claim 15.
Tatsuo teaches in Fig 6, wherein providing the device structure further comprises forming a source region (Fig 6; 26; ¶ [0077]) over a well, wherein the trench (Fig 6; 11; ¶ [0076]) is formed through the epitaxial layer (Fig 6; 24; ¶ [0077]), the well (Fig 6; 26; ¶ [0077]), and the source region (Fig 6; 28; ¶ [0077]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant’s disclosure:
Hatakeyama(US20120108043A1); A method to fabricate a stacked semiconductor device by etching a pattern in a semiconductor stack.
Kono(US9882036B2); A semiconductor device with trenches and an implantation region below.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BASEEMAH QADEER RUCKER whose telephone number is (571)272-0380. The examiner can normally be reached Monday-Friday 7:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at 5712727925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.Q.R./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
Prosecution Insights