DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-17 in the reply filed on 4/27/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2 and 7 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LEE (US 20160043119).
Regarding claim 1, LEE discloses a semiconductor device, comprising:
a semiconductor layer (the substrate 450-5, see fig 11, para 128);
a plurality of isolation trench features (D1 and D2, see fig 11, para 128 and 130) disposed in the semiconductor layer,
wherein the plurality of isolation trench features includes a first trench (the left trench D2, see fig 11, para 128) extending through an entirety of the semiconductor layer and a second trench (fig 11, D1, para 128-130) extending through a portion of the semiconductor layer and having a terminal end within the semiconductor layer (the lower end of D1 is within 450-5, see fig 11), and a third trench extending through the entirety of the semiconductor layer (the right trench D2, see fig 11, para 128-130),
wherein the second trench interposes the first trench and the third trench is a cross-sectional view (D1 is between D2, see fig 11);
a color filter over the semiconductor layer (fig 11, 416, para 105); and
a microlens disposed over the color filter (fig 11, 412, para 105).
Regarding claim 2, LEE discloses the semiconductor device of claim 1, wherein the color filter is a single color filter and is vertically over the first trench, the second trench and the third trench (416 is over D1 and both D2, see fig 11).
Regarding claim 7, LEE discloses the semiconductor device of claim 1, a control gate on a surface of the semiconductor layer, the surface opposing the color filter (the gate 472 below 450-5, para 111).
Claim(s) 1, and 3 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by SAKAMOTO (US 20240204014).
Regarding claim 1, SAKAMOTO discloses a semiconductor device, comprising:
a semiconductor layer (fig 8 and 17, 11, para 134);
a plurality of isolation trench features (trenches 14 and 13, see fig 8 and 17, 14, para 115 and 141) disposed in the semiconductor layer,
wherein the plurality of isolation trench features includes a first trench extending through an entirety of the semiconductor layer (the middle trench 13, see fig 17,para 115) and a second trench extending through a portion of the semiconductor layer and having a terminal end within the semiconductor layer (the right trench 14, which only goes partially through 11 and whose lower end is in 11, see fig 17, para 115), and a third trench extending through the entirety of the semiconductor layer (the right trench 13, see fig 17, para 115),
wherein the second trench interposes the first trench and the third trench is a cross-sectional view (the right trench 14 is between the middle 13 and the right 13, see fig 17);
a color filter (fig 17, 21, para 146) over the semiconductor layer; and
a microlens (fig 17, 24, para 143) disposed over the color filter.
Regarding claim 3, SAKAMOTO discloses the semiconductor device of claim 1, wherein the second trench extends in a first direction in a top view (the trench 14 between each section 12 extends in the y-direction in the top view of fig 8).
Claim(s) 11-16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by FUJITA (US 20220045110).
Regarding claim 11, FUJITA discloses an image sensor, comprising:
an array of lens including a first lens (the left lens 205, see fig 11, para 50) and a second lens (right lens 205, see fig 11, para 50) each disposed over a semiconductor substrate (fig 11, 201, para 46);
a first color filter (fig 11, 202, par a50) vertically under the first lens and a second color filter (fig 11, 203, para 50) vertically under the second lens;
a first deep trench isolation (DTI) feature (left isolation 212, see fig 11, para 60), a second DTI feature (middle 212, see fig 11, para 60), and a third DTI feature (right 212, see fig 11, para 60), wherein each of the first DTI feature, the second DTI feature, and the third DTI feature extend (212 extend from a top surface of 201 to 211, see fig 11) from a first surface of the semiconductor substrate (the top surface of 201, see fig 11) to an isolation region (isolation element 211, see fig 11, para 60) on a second surface of the semiconductor substrate (211 is on the bottom side of 201, see fig 11);
a first dual photodetector (DPD) vertically under the first lens and the first color filter (the left set of PD1 and PD2, see fig 11, para 57), and a second DPD vertically under the second lens and the second color filter (the right set of PD1 and PD2, see fig 11, para 57), wherein the first DPD is disposed between the first DTI feature and the second DTI feature (the left set of PD1 and PD2 are between the left 212 and the middle 212, see fig 11) and wherein the second DPD is disposed between the second DTI feather and the third DTI feature (the right set of PD1 and PD2 are between the middle 212 and the right 212, see fig 11); and
wherein the first DPD is configured to allow a photoelectric current to flow from a first photodetector of the first DPD to a second photodetector of the first DPD (charges flow between PD1 and PD2 through 240, see fig 11, para 57).
Regarding claim 12, FUJITA discloses the image sensor of claim 11, wherein
the first DPD includes a first trench isolation structure (the 220 between the left PD1 and PD2, see fig 11, para 54) extending from the first surface of the semiconductor substrate to a terminal end within the semiconductor substrate (222 as part of 220 extends from the top surface of 201 to end within 201, see fig 11) and spaced a distance from the second surface of the semiconductor substrate (the bottom end of 222 is spaced apart from the bottom surface of 201, see fig 11),
wherein the first trench isolation structure is disposed between the first photodetector and the second photodetector (220 is between PD1 and PD2, see fig 11).
Regarding claim 13, FUJITA discloses the image sensor of claim 12, wherein the second DPD is configured to allow a photoelectric current to flow from a third photodetector of the second DPD (the right PD1, see fig 11, para 57) to a fourth photodetector (the right PD2, see fig 11, para 57) of the second DPD (there is a 240 between the right PD1 and PD2 to allow charge transfer, see fig 11, para 57).
Regarding claim 14, FUJITA discloses the image sensor of claim 13, wherein
the second DPD includes a second trench isolation structure (the 220 between the right PD1 and PD2, see fig 11, para 54) extending from the first surface of the semiconductor substrate to a terminal end within the semiconductor substrate (222 as part of 220 extends from the top surface of 201 to end within 201, see fig 11) and spaced another distance from the second surface of the semiconductor substrate (the bottom end of 222 is spaced apart from the bottom surface of 201, see fig 11),
wherein the second trench isolation structure is disposed between the third photodetector and the fourth photodetector (220 is between PD1 and PD2, see fig 11).
Regarding claim 15, FUJITA discloses the image sensor of claim 14, wherein the first trench isolation structure provides an interface between the first and second photodetectors of the first DPD extending in an x-direction (as a 3D object, 220 extends in the x-direction, whichever direction that is) and wherein the second trench isolation structure provides an interface between the third and fourth photodetectors of the second DPD extending in a y-direction (as a 3D object, 220 extends in the y-direction, whichever direction that is).
Regarding claim 16, FUJITA discloses the image sensor of claim 11, wherein the first lens and the second lens provide an aperture (the area in the middle of fig 6 which will be between the 4 lenses on each of the PD1 and PD2 pairs, see fig 3 and 6, para 37), and wherein in a top view a first control gate (G1) and a second control gate (G2) are provided in a first side and an opposing second side of the aperture (gates of the transistors 230 in pixels on the top-left and bottom-right of fig 6, see fig 6 and 7, para 49).
Claim(s) 21-23 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by AHN (US 20160111461).
Regarding claim 21, AHN discloses an image sensor, comprising:
a semiconductor layer (the substrate 710, see fig 4, para 99) having a first surface (the top surface of 710, see fig 4) and a second surface (the bottom surface of 710, see fig 4), the second surface opposing the first surface; a plurality of isolation structures (the trench isolation structures 510 and 710, see fig 4, para 103) within the semiconductor layer,
wherein the plurality of isolation structures includes:
a first trench (the left DTI 510, see fig 4, para 103) extending through the semiconductor layer from the first surface of the semiconductor layer to an isolation feature disposed on the second surface (510 extends from a top surface of 710 to an isolation feature 520, see fig 4, para 103 and 88);
a second trench extending through a portion of the semiconductor layer and having a terminal end within the semiconductor layer (750 extends partially through 710, see fig 4, 750, para 103), and
a third trench (the right DTI 510, see fig 4, para 103) extending through the semiconductor layer from the first surface of the semiconductor layer to another isolation feature disposed on the second surface (710 extends from a top surface of 710 to the right isolation feature 520, see fig 4, para 103);
wherein the second trench interposes the first trench and the third trench in a cross-sectional view (750 is between the left and right 510, see fig 4), and
wherein a transistor element is disposed on the second surface of the semiconductor layer between the isolation feature and the another isolation feature (the transistor SX including SG is between the two trenches 510 horizontally, see fig 4, para 157).
Regarding claim 22, AHN discloses the image sensor of claim 21, further comprising: a first color filter over the second trench (fig 4, 703, para 100).
Regarding claim 23, AHN discloses the image sensor of claim 22, wherein the first color filter extends over the first trench (703 extends over 510, see fig 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 20160043119) in view of IM (US 20200251512).
Regarding claim 8, LEE discloses the semiconductor device of claim 7.
LEE fails to explicitly disclose a device, wherein the control gate includes a dual gate.
IM teaches a device, wherein the control gate includes a dual gate (DCG 35 can be a dual gate, see fig 3, para 20).
LEE and IM are analogous art because they both are directed towards semiconductor photodiode devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LEE with the dual gate of IM because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LEE with the dual gate of IM in order to increase efficiency (see IM para 53).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over LEE (US 20160043119) in view of IM (US 20200251512) in view of LEE 862 (US 20210335862).
Regarding claim 9, LEE and IM disclose the semiconductor device of claim 8.
LEE further discloses, further comprising: a second control gate and a third control gate on the surface of the semiconductor layer (each sub-pixel R, G or B has a gate 472 below it, see fig 3 and 11, para 111).
LEE fails to explicitly disclose a device wherein the second and third control gates are single gates.
LEE 862 teaches a device wherein the second and third control gates are single gates (300 are single gates, see fig 3C, para 62).
LEE and LEE 862 are analogous art because they both are directed towards semiconductor photodiode devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of LEE with the single gates of LEE 862 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of LEE with the single gates of LEE 862 in order to improve image quality (see LEE 862 para 54).
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over SAKAMOTO (US 20240204014) in view of CHEN (US 20190379844).
Regarding claim 4, SAKAMOTO discloses the semiconductor device of claim 3, further comprising:
a first photodetector (PD between the middle trench 13 and the right trench 14, see fig 17, para 117) extending between the first trench and the second trench, and a second photodetector (the PD between the right trench 14 and the right trench 13, see fig 17, para 117) extending between the second trench and the third trench.
SAKAMOTO fails to explicitly disclose a device wherein a photocurrent from the first photodetector is operable to transfer to the second photodetector.
CHEN teaches a device wherein a photocurrent from the first photodetector is operable to transfer to the second photodetector (the current from first PD 808 can flow to second PD 810 when M0 is closed, see fig 8 and 9, para 101 and 111).
SAKAMOTO and CHEN are analogous art because they both are directed towards semiconductor photodiode devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SAKAMOTO with the photodiode current transfer of CHEN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SAKAMOTO with the photodiode current transfer of CHEN in order to improve noise performance (see CHEN para 106).
Regarding claim 5, SAKAMOTO and CHEN disclose the semiconductor device of claim 4.
SAKAMOTO further discloses a device, further comprising:
a third photodetector (the left PD, see fig 17, para 117) and a fourth photodetector (the second PD from the left, see fig 17, para 117), wherein the third photodetector and the fourth photodetector are interposed by a fourth trench (the left trench 14, see fig 17, para 115) extending through a portion of the semiconductor layer (114 extends partially through 11, see fig 17) and having a terminal end within the semiconductor layer, wherein the fourth trench extends in a second direction in a top view (each trench 14 has an extension in the x-direction in the top view of fig 8).
Claim(s) 6 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over SAKAMOTO (US 20240204014) in view of EBIKO (US 20240290802)).
Regarding claim 6, SAKAMOTO discloses the semiconductor device of claim 1.
SAKAMOTO fails to explicitly disclose a device, wherein the plurality of isolation trench features are contiguous with a metal grid disposed over the semiconductor layer and under the microlens.
EBIKO teaches a device, wherein the plurality of isolation trench features are contiguous with a metal grid disposed over the semiconductor layer and under the microlens (the trench features 54, 55 and 101 directly contact the metal film 49 under the lens 51, see fig 11, para 48 and 90).
SAKAMOTO and EBIKO are analogous art because they both are directed towards semiconductor photodiode devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SAKAMOTO with the metal grid of EBIKO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SAKAMOTO with the metal grid of EBIKO in order to prevent a reduction in the Si diffraction effect (see EBIKO para 110).
Regarding claim 10, SAKAMOTO discloses the semiconductor device of claim 1.
SAKAMOTO fails to explicitly disclose a device, wherein the isolation trench features include a dielectric liner layer and a metal layer.
EBIKO teaches a device, wherein the isolation trench features include a dielectric liner layer (fig 11, 55, para 52) and a metal layer (fig 11, 101, para 90).
SAKAMOTO and EBIKO are analogous art because they both are directed towards semiconductor photodiode devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SAKAMOTO with the dielectric liner and metal of EBIKO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SAKAMOTO with the dielectric liner and metal of EBIKO in order to prevent a reduction in the Si diffraction effect (see EBIKO para 110).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over FUJITA (US 20220045110)) in view of IM (US 20200251512) and LEE 862 (US 20210335862).
Regarding claim 17, FUJITA discloses the image sensor of claim 16, wherein in the top view of a third control gate is provided on a third side and a fourth control gate is provided on a fourth side of the aperture (gates of the transistors 230 in pixels on the bottom-left and top-right of fig 6, see fig 6 and 7, para 49).
FUJITA fails to explicitly disclose a device wherein the third control gate and the fourth control gate are dual gate structures, and
wherein G1 and G2 are each single gate structures.
IM teaches a device wherein the third control gate and the fourth control gate are dual gate structures (DCG 35 can be a dual gate, see fig 3, para 20).
FUJITA and IM are analogous art because they both are directed towards semiconductor photodiode devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of FUJITA with the dual gate of IM because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of FUJITA with the dual gate of IM in order to increase efficiency (see IM para 53).
FUJITA and IM fail to explicitly disclose a device wherein G1 and G2 are each single gate structures.
LEE 862 teaches a device wherein G1 and G2 are each single gate structures (300 are single gates, see fig 3C, para 62).
FUJITA, IM and LEE 862 are analogous art because they both are directed towards semiconductor photodiode devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of FUJITA and IM with the single gate of LEE 862 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of FUJITA and IM with the single gate of LEE 862 in order to improve image quality (see LEE 862 para 54).
Conclusion
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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