Prosecution Insights
Last updated: August 17, 2026
Application No. 18/405,951

ONE-TIME-PROGRAMMABLE MEMORY DEVICES WITH HIGH SECURITY AND METHODS OF MANUFACTURING THEREOF

Non-Final OA §102§103
Filed
Jan 05, 2024
Priority
Aug 21, 2023 — provisional 63/520,815 +1 more
Examiner
WALL, VINCENT
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
1m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
507 granted / 815 resolved
-5.8% vs TC avg
Strong +24% interview lift
Without
With
+24.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
59 currently pending
Career history
871
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
52.4%
+12.4% vs TC avg
§102
16.2%
-23.8% vs TC avg
§112
25.1%
-14.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 815 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species A1a, figure 5, claims 1-2, 4-15, and 21-26 in the reply filed on July 8, 2026 is acknowledged. Figure 11 is distinct from figure 5. Applicant’s ¶ 0062 states that figure 11 is a hybrid cross-sectional and can, e.g. may, be formed from figure 5. In addition, ¶ 0062 states that it also may, e.g. can, be formed from figures 6-10. Therefore, Examiner interprets ¶ 0062 as meaning figure 11 is distinct and mutually exclusive as it is an amalgamation of a plurality of different figures. Claim 14 is withdrawn from consideration as it requires a first resistor to be formed on the frontside of the substrate, and the second resistor on the backside of the substrate. The elected species does not teach this. Information Disclosure Statement The information disclosure statement (IDS) submitted on January 15, 2025 was considered by the examiner. Drawing Objections The drawings are objected to because: In figure 6 elements 506 and 640 are the same structure as indicated by the use of the same hash lines for each. In figure 6 elements 502 and 620 are the same structure as indicated by the use of the same hash lines for each. In figure 9 elements 520 and 522 are MD, however, in the specification at ¶ 0060 element 530 is called an MD. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Claim 1 requires “a transistor formed along the frontside surface of the substrate”. In figures 5-10 showing a transistor formed along a frontside surface of a substrate. Figures 7-8 show a substrate, but they show no features of a transistor. Figure 5 does not label any structure, or combination of structures a transistor. In fact elements 516 and 512 are labeled as gate structures. Gate structures are not transistors and represent only part of a transistor. Therefore, the limitations of claim 1 must be shown or the feature(s) canceled from the claim(s). Claim 12 requires “wherein the second resistor is coupled to the first resistor in series, and the first resistor is coupled to the transistor in series; wherein the first resistor, the second resistor, and the transistor are vertically spaced from one another.” Figures 5-10 do not show this relationship. The drawings are objected because the features of claim 12 are not shown for the same reasons as claim 1 as discussed above. No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s)s 1-2, 12, 15 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Chang et al. (US 2021/0020645 A1) (“Chang”). Regarding claim 1, Chang teaches at least in figure 2: a transistor (202) formed along a frontside surface of a substrate (201); a first fuse resistor (212b) formed in a first metallization layer (M2) that is vertically disposed with respect to the frontside surface (front of 201); and a second fuse resistor (214b) formed in a second metallization layer (M4) that is vertically disposed with respect to the frontside surface (front of 201), the first metallization layer (M2) being different from the second metallization layer (M4); wherein the second fuse resistor and the first fuse resistor are each coupled to the transistor (212b and 214b are both coupled to 202). Regarding claim 2, Chang teaches at least in figure 2: wherein the second fuse resistor, the first fuse resistor, and the transistor are coupled to each other in series (212b and 214b are in series). Regarding claim 12, Chang teaches at least in figure 2: a transistor (202), a first resistor (212b where the material making up 212b has a resistance), and a second resistor (214b where the material making up 212b has a resistance); wherein the second resistor is coupled to the first resistor in series, and the first resistor is coupled to the transistor in series (this is shown in figure 2); wherein the first resistor, the second resistor, and the transistor are vertically spaced from one another (this is shown in figure 2). Regarding claim 15, Chang teaches at least in figure 2: wherein the transistor (202) is formed along a frontside surface of a substrate (top of 201), the first resistor (212b) comprising a plurality of first metal tracks that are formed in a first one of a plurality of frontside metallization layers disposed over the frontside surface (212a-c), and the second resistor (214b) comprising a plurality of second metal tracks that are formed in a second one of the plurality of frontside metallization layers (214a-c). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4-9, 11, 13, and 21-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang. Regarding claim 4, Chang teaches at least in figure 2: wherein one of the first fuse resistor or the second fuse resistor is configured to be randomly blown, thereby permanently presenting a logic state (Because the prior art teaches the same structure it is configured to be used in the same manner; Additionally, or alternatively, the claim is directed to the use of the device.). Regarding claim 5, Chang teaches at least in figure 2: the first fuse resistor includes a first metal track, a second metal track, a third metal track, a fourth metal track, and a fifth metal track, the first to fifth metal tracks disposed in the first metallization layer and extending along a first lateral direction (Chang teaches 212b includes 212a-c in figure 3. The includes of more metal tracks is considered a duplication of metal layers making up 212a-c.), the second fuse resistor includes a sixth metal track, a seventh metal track, an eighth metal track, a ninth metal track, and a tenth metal track, the sixth to tenth metal tracks disposed in the second metallization layer and extending along the first lateral direction (Chang teaches 214b includes 214a-c in figure 3. The includes of more metal tracks is considered a duplication of metal layers making up 214a-c.) Regarding claim 6, Chang teaches at least in figure 2: wherein the first metal track has a first end and a second end along the first lateral direction, wherein the first end of the first metal track is interposed between the second metal track and the third metal track along a second lateral direction perpendicular to the first lateral direction, and wherein the second end of the first metal track is interposed between the fourth metal track and the fifth metal track along the second lateral direction (as shown in figure 5 above, the first metal track can be 212a or 212c and the second metal track can be 212c or 212a and the third metal track 212b is between 212a and 212c. The fourth and fifth metal tracks are the duplication of elements which 212a-c can be between). Regarding claim 7, Chang teaches at least in figure 2: wherein the sixth metal track has a first end and a second end along the first lateral direction, wherein the first end of the sixth metal track is interposed between the seventh metal track and the eighth metal track along the second lateral direction, and wherein the second end of the sixth metal track is interposed between the ninth metal track and the tenth metal track along the second lateral direction (claim 7 is obvious for the same reason as claim 6 above however it is regard to 214a-c). Regarding claim 8, Chang teaches at least in figure 2: wherein the second metal track and the third metal track each have a first portion extending away from the first end of the first metal track along the first lateral direction, and wherein the seventh metal track and the eighth metal track each have a second portion extending away from the first end of the sixth metal track along the first lateral direction (as each of the metal tracks are three-dimensional objects they will each extend along a first lateral direction). Regarding claim 9, Chang teaches at least in figure 2: wherein the first portion and the second portion are coupled to each other through at least a plurality of via structures (as shown in figure 2 fuses 214b and 212b are connected by vias 208_3 and 208_4). Regarding claim 11, Chang teaches at least in figure 2: wherein the first portion and the second portion are disposed in a first area of the substrate spaced away from a second area of the substrate, and wherein at least the transistor is formed in the second area (when viewed in a planar view it would be obvious that the transistor would be formed in a second area of the substrate and the fuses would be formed in a first area of the substrate. This would be obvious based upon the size of the transistor and the size and location of the fuses). Regarding claim 13, Chang teaches at least in figure 2: Claim 13 is rejected for the same reason as claim 4 above. Regarding claim 21, Claim 21 contains the subject matter of claims 1-2, and 4, and is rejected for the same reasons. Regarding claim 22, Claim 22 contains the subject matter of claim 5, and is rejected for the same reasons. Regarding claim 23, Claim 23 contains the subject matter of claim 6, and is rejected for the same reasons. Regarding claim 24, Claim 24 contains the subject matter of claim 7, and is rejected for the same reasons. Regarding claim 25, Claim 25 contains the subject matter of claim 8, and is rejected for the same reasons. Regarding claim 26, Claim 26 contains the subject matter of claim 9, and is rejected for the same reasons. Allowable Subject Matter Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 10, Chang does not teach: wherein each of the plurality of via structures extends through a backside surface of the substrate opposite to the frontside surface (The figures of Chang do not teach utilizing the backside of the substrate). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINCENT WALL/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Jan 05, 2024
Application Filed
May 31, 2024
Response after Non-Final Action
Jul 23, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
86%
With Interview (+24.3%)
2y 9m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 815 resolved cases by this examiner. Grant probability derived from career allowance rate.

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