DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
2. The Amendments filed July 1st, 2026, in response to the Non-Final Office Action mailed 04/01/2026 are noted.
Applicants’ amendments to the claims are noted.
3. Claims 1-20 remain pending in the application.
4. Claims 1-20 have been fully considered in examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Strand (U.S. PG Pub No US2021/0090641A1).
Regarding claim 1, Strand teaches a method [see title, 0081, 0150-0156], comprising:
applying a first pulse (first writing voltage pulse used to generate first logic state [0151-0152]) to a ferroelectric memory device (540 comprising 205 comprising 240) fig. 5 [0081, 0085-0086, 0125] (see also fig. 2), wherein the first pulse (used to write first set of logic states) [0150-0151] has a first voltage magnitude (each reading/writing operation is associated with a non-zero voltage pulse [0081, 0150-0155]);
measuring a memory window metric (difference between a first and second logic state [0152-0155]) of the ferroelectric memory device (540 comprising 205 comprising 240), wherein measuring the memory window metric (difference between a first and second logic state [0152, 0155]) comprises measuring a difference [0155] between a first current amount (implied measurement of current through voltage of first logic state [0150-0152]) generated by the ferroelectric memory device (540 comprising 205 comprising 240) in a first logic state [0150-0152] and a second current amount (implied measurement of current through voltage [0152-0155] of second logic state) generated by the ferroelectric memory device (540 comprising 205 comprising 240) in a second logic state [0152-0155];
applying a second pulse (non-zero voltage pulse associated with third logic state [0154-0155]) to the ferroelectric memory device (540 comprising 205 comprising 240), wherein the second pulse (non-zero voltage pulse associated with third logic state [0154-0155]) has a second voltage magnitude (second offset reference voltage [0155]), wherein the second voltage magnitude (second offset reference voltage [0155]) is determined based at least in part on the measured memory window metric (difference between a first and second logic state [0152-0155]) (each prior logic state may be used to inform measurement operations, such as computed differences [0155], between associated logic states [0154-0155] and subsequently generated logic states [0155] by distinct voltage pulses [0081, 0150-155]).
Regarding claim 10, Strand teaches a non-transitory computer-readable medium storing program instructions (instructions for application of voltage pulses [0081, 0150-0156]), which, when executed by a processor (540 comprising processor) fig. 5 [0081, 0085-0086, 0125, 0128] operatively coupled to the non-transitory computer-readable medium (memory device 205 of 540) fig. 5 [0081, 0085-0086, 0125] (see also fig. 2), cause the processor [0128] to perform a method [see title, 0081, 0150-0156] comprising:
applying a first pulse (first writing voltage pulse used to generate first logic state [0151-0152]) to a ferroelectric memory device (540 comprising 205 comprising 240) fig. 5 [0081, 0085-0086, 0125] (see also fig. 2), wherein the first pulse (used to write first set of logic states) [0150-0151] has a first voltage magnitude (each reading/writing operation is associated with a non-zero voltage pulse [0081, 0150-0155]);
measuring a memory window metric (difference between a first and second logic state [0152-0155]) of the ferroelectric memory device, wherein measuring the memory window metric (difference between a first and second logic state [0152, 0155]) comprises measuring a difference between a first current amount (implied measurement of current through voltage of first logic state [0150-0152]) generated by the ferroelectric memory device (540 comprising 205 comprising 240) in a first logic state [0150-0152] and a second current amount (implied measurement of current through voltage [0152-0155] of second logic state) generated by the ferroelectric memory device (540 comprising 205 comprising 240) in a second logic state [0152-0155];
applying a second pulse (non-zero voltage pulse associated with third logic state [0154-0155]) to the ferroelectric memory device (540 comprising 205 comprising 240), wherein the second pulse (non-zero voltage pulse associated with third logic state [0154-0155]) has a second voltage magnitude (second offset reference voltage [0155]), wherein the second voltage magnitude (second offset reference voltage [0155]) is determined based at least in part on the measured memory window metric (difference between a first and second logic state [0152-0155]) (each prior logic state may be used to inform measurement operations, such as computed differences [0155], between associated logic states [0154-0155] and subsequently generated logic states [0155] by distinct voltage pulses [0081, 0150-155]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7 and 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over Muller (U.S. PG Pub No US2021/0125656A1) (of record) in view of Strand (U.S. PG Pub No US2021/0090641A1).
Regarding claim 1, Muller teaches a method [see title, 0002]:
applying a first pulse (510-1 with 510-2) fig. 5E [0168-0169] to a ferroelectric memory device (100 comprising memory cells 102) fig. 1A [0048, 0145, 0155] (memory cells comprise ferroelectric material [0033]), wherein the first pulse (510-1 with 510-2) has a first voltage magnitude (Ap-1) [0168];
measuring a memory window metric (420) fig. 4E [0144-0145] of the ferroelectric memory device (100/102) (implied measurement of threshold voltage [0024-0025] determining memory window [0026] obtained by measurement of time dependence of voltage drop [0174, 0022-0026] for each 510 voltage-pulse [0165-0167]);
applying a second pulse (510-3) fig. 5E [0168-0169] to the ferroelectric memory device (100/102), wherein the second pulse (510-3) has a second voltage magnitude (Ap-3) [0168], wherein the second voltage magnitude (Ap-3) is determined [0156, 0168] based at least in part on the measured memory window metric (relative amplitude [0156, 0168] and polarity [0163] of each pulse 510 resulting in particular time dependent voltage drop [0174, 0022-0026] informs/determines amplitude [0168] and polarity [0163] of subsequent pulses 510 until “the memory cell 102 is shifted to a predefined value associated with the respective threshold voltage” [0145] – until the predefined threshold voltages/memory window is/are reached [0145]).
However, Muller does not explicitly disclose wherein measuring the memory window metric (420) comprises measuring a difference between a first current amount generated by the ferroelectric memory device (100 comprising memory cells 102) in a first logic state and a second current amount generated by the ferroelectric memory device (100 comprising memory cells 102) in a second logic state.
Strand teaches a method [see title, 0081, 0150-0156] wherein measuring the memory window metric (difference between a prior and subsequent, i.e, “second” and “third” logic state [0152-0155]) comprises measuring a difference [0155] between a first current amount (implied measurement of current through voltage of “second set of logic states” [0154-0155]) generated by the ferroelectric memory device (540 comprising 205 comprising 240) fig. 5 [0081, 0085-0086, 0125] (see also fig. 2) in a first logic state (first/ “second set of logic states” [0154-0155]) and a second current amount (implied measurement of current through voltage of “third set of logic states” [0154-0155]) generated by the ferroelectric memory device (540 comprising 205 comprising 240) in a second logic state (“third set of logic states” [0154-0155]).
Therefore, it would have been obvious to someone of ordinary skill in art before the effective filing date of the claimed invention to have modified the method of Muller to specifically include the measurement procedure of computing the difference of current-voltage responses of multiple logic states [0154-0155] in order to successfully confirm whether the logic states of the memory device are desirably configured [0155] for the intended memory functions [0155-0156], as taught by Strand.
Regarding claim 2, Muller in view of Strand teaches the method [see title, 0002] of claim 1. Muller also teaches wherein the second voltage (Ap-3) fig. 5E [0168] magnitude is different [0168] from the first voltage magnitude (Ap-1) fig. 5E [0168] (individual amplitudes Ap-n’s may be less than or greater than each other [0168]).
Regarding claim 3, Muller in view of Strand teaches the method [see title, 0002] of claim 2. Muller also teaches wherein the second voltage magnitude (Ap-3) fig. 5E [0168] is larger than the first voltage magnitude (Ap-1) fig. 5E [0168] (individual amplitudes Ap-n’s may be less than or greater than each other [0168], i.e, Ap-1 voltage may be lower magnitude than Ap-3 [0168]).
Regarding claim 4, Muller in view of Strand teaches the method [see title, 0002] of claim 1. Muller also teaches wherein the first pulse (510-1 with 510-2) fig. 5E [0168-0169] comprises a first sub-pulse (510-1) of a first (positive) polarity and a second sub-pulse (510-2) of a second (negative) polarity opposite the first (positive) polarity [0165-0167, 0174].
Regarding claim 5, Muller in view of Strand teaches the method [see title, 0002] of claim 1. Muller also teaches further comprising iteratively (with “each” pulse 510 application [0163, 0174]) measuring the memory window metric state of memory window (420) fig. 4E [0144-0149] (implied measurement of threshold voltage [0024-0025] determining memory window [0026] obtained by measurement of time dependence of voltage drop [0174, 0022-0026] for each 510 voltage-pulse [0165-0167, 0174]) and applying a subsequent pulse (Ap-n+1) [0153] to the ferroelectric memory device (100/102) [0048, 0033], wherein the subsequent pulse (Ap-n+1) has a subsequent voltage magnitude (Ap+1) [0153, 0165-0168] determined based at least in part on the measured memory window metric (420) (relative amplitude [0156, 0168] and polarity [0163] of each pulse 510 resulting in particular time dependent voltage drop [0174] informs/determines amplitude [0168] and polarity [0163] of subsequent pulses 510 until “the memory cell 102 is shifted to a predefined value associated with the respective threshold voltage” [0145] – until the predefined threshold voltages/memory window is/are reached [0145]).
Regarding claim 6, Muller in view of Strand teaches the method [see title, 0002] of claim 5. Muller also teaches wherein the step of measuring the memory window metric (implied measurement of threshold voltage [0024-0025] determining memory window [0026] obtained by measurement of time dependence of voltage drop [0174, 0022-0026] for each 510 voltage-pulse [0165-0167, 0174]) and the step of applying the subsequent pulse (Ap-n+1) [0153] to the ferroelectric memory device (100/102) [0048, 0033] are iteratively performed until the measured memory window metric (420) [0163, 0144, 0026] reaches a threshold (precondition signal 110p [0145] comprising voltage pulses 510 [0155-0156] is applied until memory window 420, defined by actual relative threshold voltages [0145], “of the memory cell 102 is shifted to a predefined value associated with the respective threshold voltage” [0145] – until the predefined threshold voltages/memory window is/are reached [0145]).
Regarding claim 7, Muller in view of Strand teaches the method [see title, 0002] of claim 6. Muller also teaches further comprising:
in response to the measured memory window metric (420) [0145] not reaching the threshold (“predefined value” of threshold [0145]), changing the subsequent voltage magnitude (Ap-n+1 magnitude) [0153, 0168] of the subsequent pulse (Ap-n+1) in the next iteration (each of the subsequent pulses 510 may have differing voltage amplitudes [0168] and polarities [0163] relative to an earlier pulse 510).
Regarding claim 10, Muller teaches a non-transitory computer-readable medium (110) fig. 1 [0057] storing program instructions [0057, 0027], which, when executed by a processor [0030] operatively coupled to (integrated with) [0030, 0057] the non-transitory computer-readable medium (110), cause the processor to perform a method [0002, 0055-0059] comprising:
applying a first pulse (510-1 with 510-2) fig. 5E [0168-0169] to a ferroelectric memory device (100 comprising memory cells 102) fig. 1A [0048, 0145, 0155] (memory cells comprise ferroelectric material [0033]), wherein the first pulse (510-1 with 510-2) has a first voltage magnitude (Ap-1) [0168];
measuring a memory window metric (420) fig. 4E [0144-0145] of the ferroelectric memory device (100/102) (implied measurement of threshold voltage [0024-0025] determining memory window [0026] obtained by measurement of time dependence of voltage drop [0174, 0022-0026] for each 510 voltage-pulse [0165-0167]);
applying a second pulse (510-3) fig. 5E [0168-0169] to the ferroelectric memory device (100/102), wherein the second pulse (510-3) has a second voltage magnitude (Ap-3) [0168], wherein the second voltage magnitude (Ap-3) is determined [0156, 0168] based at least in part on the measured memory window metric (relative amplitude [0156, 0168] and polarity [0163] of each pulse 510 resulting in particular time dependent voltage drop [0174, 0022-0026] informs/determines amplitude [0168] and polarity [0163] of subsequent pulses 510 until “the memory cell 102 is shifted to a predefined value associated with the respective threshold voltage” [0145] – until the predefined threshold voltages/memory window is/are reached [0145]).
However, Muller does not explicitly disclose wherein measuring the memory window metric (420) comprises measuring a difference between a first current amount generated by the ferroelectric memory device (100 comprising memory cells 102) in a first logic state and a second current amount generated by the ferroelectric memory device (100 comprising memory cells 102) in a second logic state.
Strand teaches a method [see title, 0081, 0150-0156] wherein measuring the memory window metric (difference between a prior and subsequent, i.e, “second” and “third” logic state [0152-0155]) comprises measuring a difference [0155] between a first current amount (implied measurement of current through voltage of “second set of logic states” [0154-0155]) generated by the ferroelectric memory device (540 comprising 205 comprising 240) fig. 5 [0081, 0085-0086, 0125] (see also fig. 2) in a first logic state (first/ “second set of logic states” [0154-0155]) and a second current amount (implied measurement of current through voltage of “third set of logic states” [0154-0155]) generated by the ferroelectric memory device (540 comprising 205 comprising 240) in a second logic state (“third set of logic states” [0154-0155]).
Therefore, it would have been obvious to someone of ordinary skill in art before the effective filing date of the claimed invention to have modified the method of Muller to specifically include the measurement procedure of computing the difference of current-voltage responses of multiple logic states [0154-0155] in order to successfully confirm whether the logic states of the memory device are desirably configured [0155] for the intended memory functions [0155-0156], as taught by Strand.
Regarding claim 11, Muller in view of Strand teaches the non-transitory computer-readable medium (110) fig. 1 [0057] of claim 10. Muller also teaches wherein the second voltage (Ap-3) fig. 5E [0168] magnitude is different [0168] from the first voltage magnitude (Ap-1) fig. 5E [0168] (individual amplitudes Ap-n’s may be less than or greater than each other [0168]).
Regarding claim 12, Muller in view of Strand teaches the non-transitory computer-readable medium (110) fig. 1 [0057] of claim 10. Muller also teaches wherein the first pulse (510-1 with 510-2) fig. 5E [0168-0169] comprises a first sub-pulse (510-1) of a first (positive) polarity and a second sub-pulse (510-2) of a second (negative) polarity opposite the first (positive) polarity [0165-0167, 0174].
Regarding claim 13, Muller in view of Strand teaches the non-transitory computer-readable medium (110) fig. 1 [0057] of claim 10. Muller also teaches wherein the method [0002] further comprises iteratively (with “each” pulse 510 application [0163, 0174]) measuring the memory window metric state of memory window (420) fig. 4E [0144-0149] (implied measurement of threshold voltage [0024-0025] determining memory window [0026] obtained by measurement of time dependence of voltage drop [0174, 0022-0026] for each 510 voltage-pulse [0165-0167, 0174]) and applying a subsequent pulse (Ap-n+1) [0153] to the ferroelectric memory device (100/102) [0048, 0033], wherein the subsequent pulse (Ap-n+1) has a subsequent voltage magnitude (Ap+1) [0153, 0165-0168] determined based at least in part on the measured memory window metric (420) (relative amplitude [0156, 0168] and polarity [0163] of each pulse 510 resulting in particular time dependent voltage drop [0174] informs/determines amplitude [0168] and polarity [0163] of subsequent pulses 510 until “the memory cell 102 is shifted to a predefined value associated with the respective threshold voltage” [0145] – until the predefined threshold voltages/memory window is/are reached [0145]).
Regarding claim 14, Muller in view of Strand teaches the non-transitory computer-readable medium (110) fig. 1 [0057] of claim 13. Muller also teaches wherein the step of measuring the memory window metric (implied measurement of threshold voltage [0024-0025] determining memory window [0026] obtained by measurement of time dependence of voltage drop [0174, 0022-0026] for each 510 voltage-pulse [0165-0167, 0174]) and the step of applying the subsequent pulse (Ap-n+1) [0153] to the ferroelectric memory device (100/102) [0048, 0033] are iteratively performed until the measured memory window metric (420) [0163, 0144, 0026] reaches a threshold (precondition signal 110p [0145] comprising voltage pulses 510 [0155-0156] is applied until memory window 420, defined by actual relative threshold voltages [0145], “of the memory cell 102 is shifted to a predefined value associated with the respective threshold voltage” [0145] – until the predefined threshold voltages/memory window is/are reached [0145]).
Regarding claim 15, Muller in view of Strand teaches the non-transitory computer-readable medium (110) fig. 1 [0057] of claim 14. Muller in view of Strand also teaches wherein the threshold [0024-0025] comprises the first current amount (‘higher current flow’, low threshold voltage state [0026]) and the second current amount (‘lower current flow’, high threshold voltage state [0026]) different from the first current amount [0026].
Regarding claim 16, Muller in view of Strand teaches the non-transitory computer-readable medium (110) fig. 1 [0057] of claim 15. Muller in view of Strand also teaches wherein the first current amount (‘higher current flow’, low threshold voltage state [0026]) is larger than the second current amount (‘lower current flow’, high threshold voltage state [0026]).
Regarding claim 17, Muller in view of Strand teaches the non-transitory computer-readable medium (110) fig. 1 [0057] of claim 16. Muller in view of Strand also teaches wherein the first current amount (‘higher current flow’, low threshold voltage state [0026]) is associated with a minimum amount of current associated with the first logic state (logic “1” state [0026]) of the ferroelectric memory device (100 comprising memory cells 102) fig. 1A [0048, 0033, 0145, 0155].
Regarding claim 18, Muller teaches a method [see title, 0002], comprising:
adapting voltage magnitudes (individual amplitudes Ap) fig. 5E [0168] of pulses (510’s) fig. 5E [0161] of a pulse train (520) fig. 5E [0161] applied to a ferroelectric memory device (100 comprising memory cells 102) fig. 1A [0048, 0145, 0155] (memory cells comprise ferroelectric material [0033]) in response to respective memory window (420) fig. 4E [0144-0145] metrics measured from the ferroelectric memory device (memory cells) [0155] after each of the applied pulses (510) (implied measurement of threshold voltage [0024-0025] determining memory window [0026] obtained by measurement of time dependence of voltage drop [0174, 0022-0026] for each 510 voltage-pulse [0165-0167, 0174]) until the measured memory window metric (420) reaches a threshold (precondition signal 110p [0145] comprising voltage pulses 510 [0155-0156] is applied until memory window 420, defined by actual relative threshold voltages [0145], “of the memory cell 102 is shifted to a predefined value associated with the respective threshold voltage” [0145] – until the predefined threshold voltages/memory window is/are reached [0145]).
However, Muller does not explicitly disclose wherein the measured memory window metric (420) comprises a difference between a first current amount generated by the ferroelectric memory device (100 comprising memory cells 102) in a first logic state and a second current amount generated by the ferroelectric memory device (100 comprising memory cells 102) in a second logic state.
Strand teaches a method [see title, 0081, 0150-0156] wherein the measured memory window metric (difference between a prior and subsequent, i.e, “second” and “third” logic state [0152-0155]) comprises a difference [0155] between a first current amount (implied measurement of current through voltage of “second set of logic states” [0154-0155]) generated by the ferroelectric memory device (540 comprising 205 comprising 240) fig. 5 [0081, 0085-0086, 0125] (see also fig. 2) in a first logic state (first/ “second set of logic states” [0154-0155]) and a second current amount (implied measurement of current through voltage of “third set of logic states” [0154-0155]) generated by the ferroelectric memory device (540 comprising 205 comprising 240) in a second logic state (“third set of logic states” [0154-0155]).
Therefore, it would have been obvious to someone of ordinary skill in art before the effective filing date of the claimed invention to have modified the method of Muller to specifically include the measurement procedure of computing the difference of current-voltage responses of multiple logic states [0154-0155] in order to successfully confirm whether the logic states of the memory device are desirably configured [0155] for the intended memory functions [0155-0156], as taught by Strand.
Regarding claim 19, Muller in view of Strand teaches the method [see title, 0002] of claim 18. Muller also teaches wherein the ferroelectric memory device (100 comprising memory cells 102) fig. 1A [0048, 0145, 0155] (memory cells comprise ferroelectric material [0033]) is a ferroelectric field-effect transistor (FeFET) [0030-0032].
Regarding claim 20, Muller in view of Strand teaches the method [see title, 0002] of claim 18. Muller also teaches wherein the ferroelectric memory device (100 comprising memory cells 102) fig. 1A [0048, 0145, 0155] comprises a hafnium-based [0033] ferroelectric material (memory cells comprise ferroelectric material such as hafnium oxide [0033]).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Muller (U.S. PG Pub No US2021/0125656A1) (of record) modified by Strand (U.S. PG Pub No US2021/0090641A1), as applied in claim 1 above, and further in view of Salahuddin (U.S. PG Pub No US2024/0136437A1) (of record).
Regarding claim 8, Muller in view of Strand teaches the method [see title, 0002] of claim 1. However, Muller does not explicitly disclose further comprising:
applying an endurance cycling pulse train to the ferroelectric memory device (100/102) [0048, 0033].
Salahuddin teaches a method [see figs. 3A-3C, 0037-0039] further comprising:
applying an endurance cycling pulse train (+/- 3V pulses) figs. 3A-3B [0037-0038] to the ferroelectric memory device (10) fig. 1 [0028].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Muller to further include the endurance testing protocol [0037-0039] of Salahuddin in order to test and ensure robust memory retention [0041] and fast reading performance [0037-0039] over possibly trillions of cycles [0005-0007], thereby verifying the applicability of the ferroelectric memory device [0041] for a variety of uses [0041], as taught by Salahuddin.
Regarding claim 9, Muller in view of Strand teaches the method [see title, 0002] of claim 1. However, Muller does not explicitly disclose further comprising applying a reading pulse train and an endurance cycling pulse train to the ferroelectric memory device (100/102) [0048, 0033], wherein the endurance cycling pulse train is interspersed with the reading pulse train.
Salahuddin teaches a method [see figs. 3A-3C, 0037-0039] further comprising:
applying a reading pulse train (Vg read, Vd read) fig. 3B [0037, 0038] and an endurance cycling pulse train (+/- 3V pulses) figs. 3A-3B [0037-0038] to the ferroelectric memory device (10) fig. 1 [0028], wherein the endurance cycling pulse train (+/- 3V pulses) is interspersed (“periodically throughout” [0038]) with the reading pulse train (Vg read, Vd read).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Muller to further include the endurance testing protocol [0037-0039] of Salahuddin in order to test and ensure robust memory retention [0041] and fast reading performance [0037-0039] over possibly trillions of cycles [0005-0007], thereby verifying the applicability of the ferroelectric memory device [0041] for a variety of uses [0041], as taught by Salahuddin.
Response to Arguments
Applicants’ arguments with respect to claim(s) 1, 10, and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ocker (U.S. PG Pub No US2023/0215481A1) (of record) teaches another example of a ferroelectric memory device with preconditioning, memory window adjustment pulse trains and endurance testing. Schenk (U.S. PG Pub No US2023/0402083A1) (of record) and remaining references made available on the PTO-892 form (of record) teach ferroelectric memory devices with various voltage pulse cycles.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 09/28/2026
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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