DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I in the reply filed on 4/8/2026 is acknowledged.
Claim Objections
Claim 1 9 and 21 objected to because of the following informalities: lines 3 of claims 1 9, and 21 disposed is spell dispsoed . Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-6, 13 and 23 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 5 recites wherein the active region has a first side and a second side abutting the first side, the first side faces the first protruding portion of the ILD, and the second side is free from facing the first protruding portion of the ILD. This is unclear since it is unclear how to define a side of a active region. Active region is typically defined as where the junction area or where functional charge carrier activity occurs. This is a nebulous structure and can have arbitrarily defined sides. It appears applicant is referring to a active region defined by the surrounding isolation structure. However, the claim as written can have an infinite number of arbitrarily defined sides which encompass the functional charge carriers.
Further recitation the first side faces the first protruding portion of the ILD, and the second side is free from facing the first protruding portion of the ILD. Is unclear since “sides” themselves do not have a single facing direction. In fact, 104s1 pointed to by applicant in figure 1A could reasonably be interpreted as having a face facing away from the protrusion since the side faces towards 114-1 and also has a face that faces away from 114-1. As an example the outer wall in a house has an outer facing surface towards the outside and interior facing face facing towards the interior; thus it is unclear how applicant is defining a facing direction of a side. It appear a single singe could face the protrusion and be free from facing the protrusion.
As to claim 6 for substantially the same reasons as claim 5 claim 6 unclear: wherein the active region has a third side opposite to the first side, and the ILD comprises a second protruding portion protruding toward the isolation structure and facing the third side of the active region. Specifically, how does one define a side of an active region and how does one define a facing direction for a side.
As to claim 13 recites wherein the active region has a first side and a second side abutting the first side, the first side faces the first recess, and the second side is free from facing the first recess and for the same reasons outlined for claim 5 the claim is unclear it is unclear how one defines a side of an active region and how one is to define a facing direction of side.
As to claim 23,It is unclear the scope of wherein the plurality of gate stack structures are arranged along a first directions. Arrange means: things placed in a specific, proper order or plans made in advance, such as organizing, settling, or preparing something. It is unclear if arranged in: the plurality of gates stack structure “arranged” along a first direction, refers to arrangement of each individual gate or the grouping of gates as a whole. Each gate individually is arranged in along all the directions since they are three dimensional objects. It appears applicant means to recite wherein the plurality of gate stack structures are arranged with respect to one another along a first direction.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 9, 10, 13, 17 and 21- 23, is/are rejected under 35 U.S.C. 102a1 as being anticipated by Huang (6406987).
a. As to claims 1, 9, and 17 Huang teaches a substrate comprising an active region (figure 10 item 10 region between the STI); a plurality of gate stack structures disposed on the active region of the substrate (items 16); an isolation structure embedded within the substrate and surrounding the active region (item 12 see figure 7 )
Referring now to FIG. 7 and by the method of this invention, more reliable interfaces A are achieved. The method consists of utilizing a SiO.sub.2 dip etch to recess the shallow trench isolation 12 to a point X below the surface of the substrate 10 and to expose the upper portion of the sidewalls of the active device areas at the interface A. Preferably the recessing is carried out using a controlled hydrofluoric (HF) acid etch or a HF vapor etch to remove about 500 to 1000 Angstroms. The Si.sub.3 N.sub.4 sidewall spacers 18, being sufficiently wide, prevent the etching from reaching the gate oxide 14 under the gate electrodes 16, that would otherwise occur. For example, the method described for forming visors in "A 2.9 um.sup.2 Embedded SRAM Cell with Co-Salicide Direct-Strap Technology for 0.18 um High Performance CMOS Logic" by K. Noda et al. in IEDM 97 of IEEE, pp. 847-850 etches the STI by about 400 Angstroms prior to forming Si.sub.3 N.sub.4 sidewall spacers and visors, and therefore the etching would also etch the gate oxide under the gate electrode.
This dip etch cause a recess further region A is a recess.
; and an interlayer dielectric (ILD) covering the plurality of gate stack structures, and the ILD comprises a first protruding portion protruding toward the isolation structure item 22 or items 22 and 20” fig .10) this protruding portion in one-to-one correspondence with wherein the isolation structure defines a first recess recessed from an upper surface of the isolation structure (figure 7 and 10).
b. As to claims 2 and 10, Huang teaches wherein each of the plurality of gate stack structures extends along a first direction, and the first protruding portion/recess of the ILD extends along the first direction ( the elements extend in all directions but the gate extends along a principal axis the same as the STI in to the page of Huang figure 7).
c. As to claim 5 and 13, Huang teaches wherein the active region has a first side (portion of item 10 adjacent to item 12 figure 10) and a second side abutting the first side ( another portion directly contacting first portion see e.g. region containing 17), the first side faces the first protruding portion of the ILD (sloped portion of item 10 adjacent to item 12 faces the recess), and the second side is free from facing the first protruding portion of the ILD. The active region can be defined as including an interfacial region between the STI and the substrate at the 16 closest to 24 in figure 15. The outer surface of that active region faces the recess and protrusion. While the top surface of the active between the two STI is free from facing the recess. The top surface abuts the side of the STI. Further into the page and out of the page is free from facing as well as a bottom outer surface of the active region all of these can be arbitrarily defined to abut the sidewall.
d. As to claim 21. Huang teaches A semiconductor device, comprising: a substrate comprising an active region (figure 7 and 10 item 17 and region under central 16); a plurality of gate stack structures disposed on the substrate (items 16); an isolation structure embedded within the substrate and surrounding the active region (item 12); an etching stop layer disposed on the substrate and the isolation structure (etching stop is an intended use and does not limit the scope (thus 14 and or item 20” can be consider a etch stopping layer), wherein the etching stop layer has a curved profile over the isolation structure see item (14 at edge due to bird beak); and an interlayer dielectric (ILD) covering the plurality of gate stack structures and the etching stop layer (see item 22).
e. As to claim 22, Huang teaches wherein the isolation structure defines a recess accommodating the etching stop layer ( the dips accommodate item 14).
f. As to claim 23, Huang teaches the gates form an array along a first direction ( figure 10 and the recess extends into the page; it also extends in the array direction).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (6406987) and Maniar (5,652,176) and Lin (5,780,348).
a. As to claim 6 and 14, Huang does not explicitly teach , wherein the active region has a third side opposite to the first side, and the ILD comprises a second protruding portion protruding toward the isolation structure and facing the third side of the active region. However, Huang figure 15 the first contact is on a n+ contact 19. Further the prior art figures of Huang, Figures 2-5, and discussion of prior art:
To continue increasing the circuit density on future Ultra Large Scale Integration (ULSI) circuits, downscaling is required on the semiconductor chips. This downscaling becomes increasingly difficult as the photolithography resolution improves and minimum feature sizes are reduced in the next generation of devices to deep submicrometer dimensions (e.g., 0.25 and 0.18 um). One method of increasing circuit density is to replace the conventional LOCOS (LOCal Oxidation of Silicon) isolation with a Shallow Trench Isolation (STI) that surrounds and electrically isolates the individual device areas on the silicon substrate. Briefly, the STI is formed by anisotropically etching trenches (with little etch bias) and filling the trenches with a chemical-vapor-deposited (CVD) oxide that is then etched back or chemically/mechanically polished (CMP) back to form a planar surface with the substrate. This replaces the LOCOS isolation which is formed by a thermal oxidation, which by its very nature, oxidizes laterally and intrudes on the device area. Another problem that limits the downscaling is the difficulty in making reliable borderless contacts to the device areas that overlap the STI to reduce the design rules (layout). When making the contact openings for the borderless contacts in an overlying ILD layer, overetching of the STI can result in exposing the shallow diffused junction in the substrate at the sidewall of the upper portion of the trench. The borderless contacts formed by a metal plug in the contact openings short the diffused junction to the substrate body destroying the intended circuit function. This borderless contact problem is best depicted in FIG. 1, in which a trench 2 containing an STI 12 is formed in a P.sup.- doped silicon substrate 10, and an N.sup.+ shallow diffused contact 19(N.sup.+) is formed in the substrate top surface. When an ILD layer 22 is deposited and a borderless contact opening 4 is etched, the STI 12 is overetched. A metal contact 24 formed in the opening 4 results in N.sup.+ contact 19 shorting to the substrate 10 across the P/N junction at point A in the trench sidewall.
Huang also call out each of the 19s to be a contact area :
The etch-back is carried out using anisotropic plasma etching in a high-density plasma (HDP) etcher using an etchant gas such as sulfur hexafluoride (SF.sub.6) that etches the Si.sub.3 N.sub.4 selectively to the underlying silicon substrate 10. A second ion implantation is then used to form source/drain contact areas 19 (N.sup.+) having a final concentration of between about 1.0 E 19 and 1.0 E 21 atoms/cm.sup.3.However, it was known at the time of filing to provide multiple junctions and multiple contacts.
Both Lin (figures 1E and 2G item 34) and Maniar (figure 9 item 60) teach forming borderless contacts for transistors at the edge of the STI and the source/drain.
Thus, since the borderless contacts are for devices as suggested by Huang Lin and Maniar are at the edge of transistors and STI, it would have been obvious to one ordinary skill in the art at the time of filing to provide another borderless contact at 19 the upper STI provided in figure 10. One would have been so motivated to provide a complete circuit for transistors allowing the external connection to both the source and drain. This second recces would in in a different STI and thus disconnected from the first.
The active region can use the interfacial side of the STI and the substrate to be a third side and it is opposite the first and faces the second protruding portion.
Claim(s) 7-8, and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable Huang in view of Brown (6144086).
a. As to claims 7 and 15, Huang teaches wherein the substrate comprises a body region (under a gate) with a first conductive type
Several methods of overcoming these problems are depicted in the prior art drawings in FIGS. 2 through 5. FIG. 2 shows a portion of an FET gate electrode 16 with a gate oxide 14 and two STI regions 12. The STI 12 is formed having portion 12' extending above the surface of the substrate 10. Silicon nitride sidewall spacers 13 are then formed on the sidewalls of portions 12' by depositing and etching back a Si.sub.3 N.sub.4 layer. Unfortunately, when the Si.sub.3 N.sub.4 spacers 13 encroach onto the device-areas, as depicted for the STI 12 on the left, the design rules must be relaxed to provide the necessary area for the device, and therefore limits the device packing density. As shown for the STI 12 on the right, if the Si.sub.3 N.sub.4 spacers do not extend over the interface at A, the STI can be overetched when the borderless contact openings are etched, causing electrical shorts between the shallow N.sup.+ doped contacts 19 and the P.sup.- substrate.
Huang does not teach the semiconductor device further comprises a doped region with the first conductive type situated under the isolation structure.
Brown teaches the semiconductor device further comprises a doped region with the first conductive type situated under the isolation structure (item 18 under the STI figure 17) with the 18 being the same conductivity as 28 the body.
N-type dopants are implanted to form the n-well 26. The resist 25 for the n-well 26 is then stripped and a resist 27 is applied and patterned to form the p-well 28. P-type dopants are then implanted to form the p-well 28 as shown in FIG. 7.
and
As the highly doped region 18 in this embodiment is a p+ region, the n-well 26 should not be implanted over the entire p+ region 18. Preferably, the n-well 26 is slightly shifted off-center, to the right as shown in FIG. 6, so that the n-well 26 does not overlap and counter-dope the p+ region 18.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to the STI of Huang as the structure include a P-type region and N-type region 30 under with the dual depth STI as suggested by Brown to reduce latchup between neighboring devices (see Title).
b. As to claims 8 and 16, Huang in view of Brown would teach wherein the doped region overlaps the first protruding portion of the ILD (the protruding portion is STI) along a second direction different from the first direction (it overlaps in a direction perpendicular to the principal surface of the substrate).
Claim(s) 1-4, and 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (20090026547) in view of Hirota (20080050886) in view of Huang.
a. As to claim 1 and 9, Lee teaches a substrate comprising an active region (figures 11 and 12 item 100 and 101b) a plurality of gate stack structures disposed on the active region of the substrate (items 110 figure 11 act as two gates and applicant does not preclude the gates being tied together ); an isolation structure embedded within the substrate and surrounding the active region (item 102);
Lee does not teach and an interlayer dielectric (ILD) covering the plurality of gate stack structures, and the ILD comprises a first protruding portion protruding toward the isolation structure.
Hirota teaches due to the filling of STI it was known for dents to form in STI (paragraphs 16-19 and figure 2C).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to have formed the isolation structures of Lee using conventional technique in the art at the time. To provide the expected outcome of filled isolation structure which would have inherently provided the dents due to the seams when filling the isolation.
Huang teaches passivating the surface of the active layer with a ILD (item 22 figure 10) to passivate the surface and to provide support for metallizations.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to have formed a ILD over the structure of Lee in view of Hirota to have passivated the surface and to provide structural support for interconnects to form integrated circuit device.
Thus, the dents would be filled by the ILD. And the ILD would have protruding portions at the dent regions the dents would be recesses in the isolation structures.
b. As to claim 2 and 10, Lee in view of Hirota and Huang would teach wherein each of the plurality of gate stack structures extends along a first direction, and the first protruding/recess/dents portion of the ILD extends along the first direction figure 8 Lee suggest the dents extend along the active regions or a first direction.
c. As to claim 3 and 11, Lee in view of Hirota and Huang suggests herein a length of the active region is less than a length of the first protruding portion of the ILD along the first direction ( the dent extends along the entire length of the isolation due to the seams the isolation is larger than the active region in the center and thus the protrusions).
d. As to claim 4 and 12, Applicant does not the term substantially.
Applicant states: Also, as used herein, the terms "substantially," "approximately" and “about” generally mean within a value or range that can be contemplated by people having ordinary skill in the art. Alternatively, the terms "substantially," "approximately" and “about” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. People having ordinary skill in the art can understand that the acceptable standard error may vary according to different technologies. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms "substantially," "approximately" or “about.”
Both definitions cannot be true the office will interpret it to mean within a value or range that can be contemplated by people having ordinary skill in the art.
However, this is largely arbitrary since even reasonable people can disagree on “substantially.”
Lee in view of Hirota and Huang can be considered to teach wherein the length of the first protruding portion of the ILD is substantially equal to a length of one of the plurality of gate stack structures along the first direction, since there is some gate length to which it is equal the protrusion or recess or in the alternative it would be nearly the same length as the gate since substantially is arbitrary.
Conclusion
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
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