DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In addressing the rejection ground, each claim may not have been separately discussed to the extent the claimed features are the same as or similar to the previously-discussed features; the previous discussion is construed to apply for the other claims in the same or similar way.
In the office action, “/” should be read as and/or as generally understood. For example, “A/B” means A and B, or A or B.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19-22, 25-34 and 36-37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Giuliano et al. (US 2014/0327479) in view of Fu et al. (US 2020/0007038).
Regarding claim 19, Giuliano discloses a power converter [e.g. figs 3-5], comprising: a clock to generate a clock signal [e.g. a signal used by the controller (see the matched below) to generate phase signals VP1/VP2/A0-A1/B0-B1]; a switched capacitor arrangement [e.g. M0-M5, C1-C3] comprising an input terminal [e.g. the node between 16 and M0] to receive an intermediate voltage [e.g. VI/5V] and an output terminal [VO] to output a second voltage, the switched capacitor arrangement to include a plurality of capacitors [e.g. C1-C3] to be coupled to a plurality of switches [e.g. M0-M5] via a corresponding plurality of nodes [e.g. the nodes among switches M0-M5]; a controller to generate one or more control signals based, at least in part, on the clock signal to control [e.g. driver set 32, the circuit (not shown) generating A0-A2, B0-B2/ the circuit (not shown) generating VP1, VP2] the plurality of stack switches to facilitate one or more state transitions between a first and a second operating states [see at least figs. 4-5] of the switched capacitor arrangement based, at least in part, on an input voltage.
Giuliano does not disclose an intermediate capacitor having a first terminal coupled to the input terminal of the switched capacitor arrangement and having a second terminal coupled to ground; and an inductor coupled between an output terminal of the power source and the first terminal of the intermediate capacitor, to form an LC filter in combination with the intermediate capacitor, wherein the LC filter is configured to induce a forward current from the power source through the inductor of the LC filter to increase the intermediate voltage to be greater than the input voltage. However, Fu discloses an intermediate capacitor [e.g. Co/Cin] having a first terminal [e.g. the upper terminal] coupled to the input terminal of the switched capacitor arrangement and having a second terminal [e.g. the lower terminal] coupled to ground; and an inductor [e.g. L1] coupled between an output terminal [e.g. Vin+; or see Vin] of a power source [e.g. Vin, noted: Vo+ after the combination, it’s the input terminal of the switched capacitor arrangement] and the first terminal of the intermediate capacitor, to form an LC filter in combination with the intermediate capacitor, wherein the LC filter is configured to induce a forward current from the power source through the inductor of the LC filter to increase the intermediate voltage to be greater than the input voltage [characteristic of a boost converter].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Giuliano in accordance with the teaching of Fu regarding a converter in order to provide a regulated voltage having good behaviors such as low forward voltage drop and fast reverse recovery [para. 0006].
Regarding claim 20, the combination discussed above discloses the power converter of claim 19, wherein the one or more control signals facilitate operation of said switched capacitor arrangement in a manner so as to control a slew rate at the input voltage [inherent, the control signals affect the charging of the intermediate capacitor, the same structure], and wherein the inductor has a first terminal [e.g. the left/right terminal] coupled to the output terminal of the voltage source and has a second terminal [e.g. the right/left terminal] coupled to the first terminal of the intermediate capacitor.
Regarding claim 21, the combination discussed above discloses the power converter of claim 19, wherein the switched capacitor arrangement comprises any one of: Ladder; Dickson; Series-Parallel; Fibonacci; or Doubler [see at least figs 3-5 Giuliano].
Regarding claim 22, the combination discussed above discloses the power converter of claim 19, wherein the switched capacitor arrangement is to be adiabatically charged.
Regarding claim 25, the combination discussed above discloses the power converter of claim 19, wherein the intermediate voltage is substantially equal to the first voltage in a shutdown state [e.g. no discharge].
Regarding claim 26, the combination discussed above discloses the power converter of claim 19, wherein the forward current causes the intermediate voltage to oscillate in a sinusoidal manner [based on the characteristic of an inductor] around an average voltage substantially equal to the input voltage.
Regarding claim 27, The combination discussed above discloses the power converter of claim 26, wherein the intermediate capacitor is to store captured charge from the oscillations of the intermediate voltage.
Regarding claim 28, the combination discussed above discloses the power converter of claim 27, wherein the intermediate capacitor is to use the captured charge to prop up voltages associated with the plurality of nodes [see at least figs 3-5 Giuliano].
Regarding claim 29, the combination discussed above discloses an integrated circuit, comprising: a clock to generate a clock signal; a switched capacitor arrangement comprising an input terminal to receive an intermediate voltage and an output terminal to output a second voltage, the switched capacitor arrangement to include a plurality of switches to be coupled to a plurality of capacitors via a corresponding plurality of nodes; a controller to generate one or more control signals based, at least in part, on the clock signal to control the plurality of switches to facilitate one or more state transitions between a first and a second operating states of the switched capacitor arrangement based, at least in part, on an input voltage provided by a power source at an output terminal of the power source; the input terminal of the switched capacitor arrangement being coupled to a first terminal of an intermediate capacitor having a second terminal coupled to ground; and an inductor coupled between the first terminal of the intermediate capacitor and the output terminal of the power source to form an LC filter in combination with the intermediate capacitor, wherein the LC filter is configured to induce a forward current from the power source through the inductor of the LC filter to increase the intermediate voltage to be greater than the input voltage. See rejection of claim 19.
Regarding claim 30, the combination discussed above discloses the integrated circuit of claim 29, further comprising a current-blocking element [e.g. D1/D2/D3/D4/S1/Q1] coupled to the inductor.
Regarding claim 31, the combination discussed above discloses the integrated circuit of claim 30, wherein the current-blocking element is a diode.
Regarding claim 32, the combination discussed above discloses the integrated circuit of claim 30, wherein the current-blocking element is a switch.
Regarding claim 33, the combination discussed above discloses the integrated circuit of claim 32, wherein the controller is configured to provide one or more control signals to the switch, wherein the one or more control signals facilitate operation of the switch to close to permit the forward current to flow through the inductor towards the switched capacitor arrangement and to open to prevent a reverse current to flow away from the switched capacitor arrangement.
Regarding claim 34, the combination discussed above discloses the integrated circuit of claim 30, wherein the current-blocking element comprises a diode and a switch [e.g. S1, D4/D2 fig. 2 Fu] connected in parallel to each other, and the current-blocking element being coupled in series between the inductor and the intermediate capacitor.
Regarding claim 36, the combination discussed above discloses the integrated circuit of claim 29, wherein the intermediate voltage primes the nodes of the switched capacitor arrangement.
Regarding claim 37, the combination discussed above discloses the integrated circuit of claim 29, wherein the one or more control signals facilitate operation of the switched capacitor arrangement so as to control a rise time of the input voltage.
Claim 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Giuliano et al. (US 2014/0327479) in view of Fu et al. (US 2020/0007038) and Giuliano (US 2013/0229841).
Regarding claim 23, the combination discussed above discloses the power converter of claim 19, except wherein the switched capacitor arrangement is to be diabatically charged. However, Giuliano discloses a switched capacitor arrangement can be either adiabatically charged or diabatically charged. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Giuliano and Fu in accordance with the teaching of Giuliano regarding a switched capacitor network provide a substitution of one known element for another to obtain predictable results.
Response to Arguments
Applicant’s arguments with respect to claim(s) 19 and 29 have been considered but are moot because the argument is in response to Mangtani reference. The new ground of rejection relies on Fu et al. (US 2020/007038), which is not specifically challenged in the argument.
In addition, Applicant argues: ‘Note how advantageous this is in that the voltage increase is "free" in that the LC filter is passive - the voltage increase doesn't need a switching power converter such as a boost converter.’ However, they are not recited in the claim.
Applicant's arguments filed 02/23/2026 have been fully considered but they are not persuasive.
Applicant argues:
‘Note that Fu's capacitor Cin couples between the plus side (input side) of the inductor L1 and ground. The minus side of the inductor L1 couples to the input terminal of the switched capacitor arrangement 114. But what is claimed herein is the opposite because claim 19 recites that the element of "the input terminal of the switched capacitor arrangement being coupled to a first terminal of an intermediate capacitor having a second terminal coupled to ground. Similarly, claim 19 now recites the element of "an inductor coupled between the first terminal of the intermediate capacitor and the output terminal of the power source." Fu cannot possibly satisfy this inductor element because Fu's inductor L1 and capacitor Cin both couple to the output terminal of the power source. Fu's inductor L1 is not "between the first terminal of the intermediate capacitor and the output terminal of the power source" as required by claim 19.
This is not merely a structural difference but instead is an inventive structural difference. For example, suppose that Fu's input voltage Vin+ jumps high: the capacitor Cin then acts as a short circuit to such a sudden voltage change. At the rising edge of the input voltage Vin+, both terminals of Fu's inductor L1 are thus grounded, there is then no voltage across Fu's inductor. 'But this is the opposite of what occurs in Applicant's LC filter because there is a voltage drop of approximately the input voltage across the LC filter's inductor at power-up as already explained in the previous response. There is thus no teaching or suggestion in Fu for the claim 19 advantageous element of "wherein the LC filter is configured to induce a forward current from the power source through the inductor of the LC filter to increase the intermediate voltage to be greater than the input voltage.
Claim 19 and its dependent claims 20-23 and 25-28 are thus allowable over the combination of Guiliano and Fu. Dependent claim 20 is also amended to recite a first and second terminal of the inductor and their relationship to the output terminal of the voltage source and the first terminal of the intermediate capacitor.
Claim 29 is amended analogously as discussed for claim 19. Claim 29 thus now recites the elements of "the input terminal of the switched capacitor arrangement being coupled to a first terminal of an intermediate capacitor having a second terminal coupled to ground" and "an inductor coupled between the first terminal of the intermediate capacitor and the output terminal of the power source to form an LC filter in combination with the intermediate capacitor, wherein the LC filter is configured to induce a forward current from the power source through the inductor of the LC filter to increase the intermediate voltage to be greater than the input voltage." Claim 29 and its dependent claims 30-34 and 36-37 are thus allowable over the combination of Guiliano and Fu for analogous reasons as discussed with regard to claim 19.’
However, the matching element for the intermediate capacitor is Co or Cin, not just Cin. In addition, both Co and Cin satisfy the limitation, “an inductor coupled between the first terminal of the intermediate capacitor and the output terminal of the power source”, because Fu discloses L1 is coupled between the first terminal [e.g. the upper terminal] of the intermediate capacitor [e.g. Co/Cin] and the output terminal [e.g. Vin+] of the power source [Vin], see at least figs 1-2 of Fu. In addition, at least figs 1-2 of Fu discloses the input terminal of the switched capacitor arrangement being coupled to a first terminal [e.g. the upper terminal] of an intermediate capacitor [e.g. Co/Cin (e.g. coupled via L1, S1, D1)] having a second terminal [e.g. the lower terminal] coupled to ground.
Regarding claim 20, the combination discloses wherein the inductor has a first terminal [e.g. the left/right terminal] coupled to the output terminal of the voltage source and has a second terminal [e.g. the right/left terminal] coupled to the first terminal of the intermediate capacitor [e.g. Co/Cin Fu].
Regarding claim 29, which is amended analogously as discussed for claim 19, Fu discloses “the input terminal of the switched capacitor arrangement being coupled to a first terminal of an intermediate capacitor having a second terminal coupled to ground" and "an inductor coupled between the first terminal of the intermediate capacitor and the output terminal of the power source to form an LC filter in combination with the intermediate capacitor, wherein the LC filter is configured to induce a forward current from the power source through the inductor of the LC filter to increase the intermediate voltage to be greater than the input voltage." Please see the discussion in claim 19.
Regarding the dependent claims, Applicant’s arguments are based on the arguments discussed above from claims 19 or 29. As discuss above, claims 19 and 29 are unpatentable at this point. Accordingly, the dependent claims are unpatentable at this point.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICK C CHEN whose telephone number is (571)270-7207. The examiner can normally be reached M-F Flexible 8:00-16:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PATRICK C CHEN/Primary Examiner, Art Unit 2836
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