DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 16, there is insufficient antecedent basis for the limitation “the bias waveform voltage”. For the purpose of this examination, the examiner assumes claim 16 is dependent on claim 9, which provides the needed antecedent basis.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office Action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 7-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cui et al. (US20220399183).
Regarding claim 1, Cui discloses a method for generating a bias voltage (claim 10), the method comprising: generating a radio frequency (RF) sinusoidal wave voltage (claim 10); generating a DC square wave voltage (claim 10); forming a bias waveform by synchronizing the RF sinusoidal wave voltage and the DC square wave voltage (claim 10; Fig. 6A); and providing the bias waveform to a bottom electrode of a plasma processing system (Figs. 2B and 6A; claim 10).
Regarding claim 2, Cui discloses wherein the RF sinusoidal wave voltage and the DC square wave voltage have a same frequency (paragraph 0065).
Regarding claim 3, Cui discloses wherein the same frequency is in a range of 50 kHz to 500kHz (paragraph 0065).
Regarding claim 4, Cui discloses wherein the RF sinusoidal wave voltage and the DC square wave voltage are synchronized at a same phase (Fig. 6A).
Regarding claim 7, Cui discloses wherein the plasma processing system uses continuous wave plasma processing (Fig. 6A and paragraph 0066).
Regarding claim 8, the limitation recited in the “wherein” clause in the method claim simply expresses the intended result of the recited process; therefore, it is not accorded patentability weight. See MPEP 2111.04.
Regarding claim 9, Cui discloses a method for plasma processing (abstract), the method comprising: generating a bias waveform voltage by synchronizing a pulsed DC voltage and an RF sinusoidal wave voltage at a single frequency (claim 10 and paragraph 0065); generating a plasma in a plasma processing chamber by providing source power to a top electrode of the plasma processing chamber and providing the bias waveform voltage to a bottom electrode of the plasma processing chamber (paragraph 0023 and Fig. 2B); and controlling an ion energy distribution of the plasma with the bias waveform voltage (paragraph 0023).
Regarding claim 10, Cui discloses wherein controlling the ion energy distribution of the plasma with the bias waveform voltage comprises adjusting an amplitude of the pulsed DC voltage (paragraph 0023).
Regarding claim 11, Cui discloses wherein adjusting the amplitude of the pulsed DC voltage controls a location of a peak energy of the ion energy distribution (paragraph 0023).
Regarding claim 12, Cui discloses wherein controlling the ion energy distribution of the plasma with the bias waveform voltage comprises adjusting an amplitude of the RF sinusoidal wave voltage (paragraph 0023).
Regarding claim 13, Cui discloses wherein adjusting the amplitude of the RF sinusoidal wave voltage controls a width of an ion energy spread of the ion energy distribution (paragraph 0023).
Regarding claim 14, Cui discloses wherein controlling the ion energy distribution of the plasma with the bias waveform voltage comprises adjusting duty cycles of the RF sinusoidal wave voltage and the pulsed DC voltage (paragraphs 0023 and 0063).
Regarding claim 15, Cui discloses wherein adjusting the duty cycles of the RF sinusoidal wave voltage and the pulsed DC voltage controls an ion flux of the ion energy distribution (paragraphs 0023, 0058 and 0063).
Regarding claim 16, Cui discloses wherein the bias waveform voltage comprises sinusoidal horizontal segments between vertical segments in a graph of voltage versus time (Fig. 6A).
Regarding claim 17, Cui discloses a method for plasma processing (abstract), the method comprising: providing a substrate into a plasma processing chamber (paragraph 0021 and Fig. 2B); generating a plasma in the plasma processing chamber by providing source power to a top electrode of the plasma processing chamber (paragraph 0023 and Fig. 2B); biasing a bottom electrode of the plasma processing chamber by providing pulsed DC voltage to the bottom electrode (paragraph 0037 and Fig. 2B); and compensating surface charge on the substrate by providing RF sinusoidal wave voltage to the bottom electrode, the pulsed DC voltage and the RF sinusoidal wave voltage having a shared frequency (paragraphs 0050 and 0065, and Fig. 2B).
Regarding claim 18, Cui discloses wherein the shared frequency of the pulsed DC voltage and the RF sinusoidal wave voltage is in a range of 50 kHz to 500kHz (paragraph 0065).
Regarding claim 19, Cui discloses wherein the pulsed DC voltage is modulated to set a peak ion energy for an ion energy distribution of the plasma (paragraph 0023).
Regarding claim 20, Cui discloses while the pulsed DC voltage is on, a voltage of the substrate is kept constant by the RF sinusoidal wave voltage (paragraphs 0065-0066).
Claims 1 and 5-8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US20240128055).
Regarding claim 1, Kim discloses a method for generating a bias voltage (abstract), the method comprising: generating a radio frequency (RF) sinusoidal wave voltage (paragraph 0075; Figs. 1A and 5A); generating a DC square wave voltage (paragraph 0075; Figs. 1A and 5A); forming a bias waveform by synchronizing the RF sinusoidal wave voltage and the DC square wave voltage (paragraph 0075; Figs. 1A and 5A); and providing the bias waveform to a bottom electrode of a plasma processing system (paragraph 0075; Figs. 1A and 5A).
Regarding claim 5, Kim discloses wherein the RF sinusoidal wave voltage and the DC square wave voltage are synchronized at different phases (paragraph 0075; Figs. 1A and 5A).
Regarding claim 6, Kim discloses wherein the plasma processing system uses pulsed plasma processing (paragraph 0087; Fig. 5A).
Regarding claim 7, Kim discloses wherein the plasma processing system uses continuous wave plasma processing (paragraph 0087; Fig. 9D).
Regarding claim 8, the limitation recited in the “wherein” clause in the method claim simply expresses the intended result of the recited process; therefore, it is not accorded patentability weight. See MPEP 2111.04.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIONG-PING LU whose telephone number is (571) 270-1135. The examiner can normally be reached on M-F: 9:00am – 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua L Allen, can be reached at telephone number (571)270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JIONG-PING LU/
Primary Examiner, Art Unit 1713