DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SEMICONDUCTOR DEVICE WITH THERMAL VIA
Election/Restrictions
Applicant’s election of Invention I, claims 1-17 in the reply filed on 4/2/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-17 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Cheng (US 10854530), hereinafter Cheng..
Regarding claim 1, Cheng (US 10854530) teaches a semiconductor device (100, see Figure 1 and Col. 3, lines 12-15), comprising:
a semiconductor substrate (110, described as “chip 102 is formed on substrate 110” and is made of semiconductor material such as “silicon” or “GaAs” etc. – see Col. 3, lines 32-50), comprising at least one active component {Col. 4, lines 45-56 describes "components formed on or at the vicinity of the chip's substrate, such as semiconductor devices (e.g., transistors)"};
an interconnect {116, described as "multilevel metallization layers 116" which “propagate electrical signals across each chip” in Col. 4, lines 8-22}, disposed over and electrically coupled to the at least one active component {Col. 4, lines 8-22}; and
at least one thermal via {148A described as "Thermally conductive TOV and/or TSV 148A dissipates heat" in Col. 5, lines 48-52; also see Col. 2, lines 26-32}, penetrating through (best seen in Figure 1) the interconnect (116) and thermally coupled to the at least one active component (Col. 5, lines 28-32),
wherein a thermal conductivity of the at least one thermal via (which may be made of highly thermally conductive material such as “copper” – see Col. 12, lines 30-41) is different (see below) than a thermal conductivity of a dielectric layer {126, described as "dielectric layer 126" for which material may be "silicon oxide" and/or "silicon nitride" in Col. 4, lines 19-31} of the interconnect.
Note that as the materials used are of significantly different thermal conductivities, and it is specifically taught that thermal via is designed for improved heat transfer, it is inherent that “a thermal conductivity of the at least one thermal via is different than a thermal conductivity of a dielectric layer of the interconnect”
Regarding claim 10, it is substantially similar to claim 1 except that instead of one substrate, two similar substrates that are substantially similar are stacked. It would have been obvious to one of ordinary skill in the art to as the product is considered to be a duplication of parts that has no patentable significance unless a new unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960), MPEP 2144.04.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AJAY ARORA whose telephone number is (571)272-8347. The examiner can normally be reached 9 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached at 5712721736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AJAY ARORA/Primary Examiner, Art Unit 2892
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