DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Election/Restrictions
5. Applicant’s election without traverse of Species I (Figures 1-3) in the reply filed on 6/23/2026 is acknowledged.
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/23/2026.
Specification
6. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
“Method for Forming an MRAM Semiconductor Structure with Reverse Etching of the Memory Array Region”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1-3 and 5-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen, Hsia-Wei et al. (Pub No. US 20200127053 A1) (hereinafter, Chen).
Re Claim 1, (Original) Chen teaches a method for forming a semiconductor structure, comprising:
Chen, Fig 12: Dielectric layer being applied over memory array region and peripheral region
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providing a substrate (Memory region/peripheral region; 502/506; Fig 12; ¶[0054]) having a memory array region (Memory region; 502; Fig 12; ¶[0054]) and a peripheral region (Peripheral region; 506; Fig 12; ¶[0054]) thereon;
forming a memory structure (Memory cell structures; 102a/102b; Fig 12; ¶[0033]) on the substrate within the memory array region,
Chen, Fig 11: Step height illustrated between memory array and peripheral region
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wherein a step height (Step height of 102a/102b (not labelled); Fig 11) is formed between the memory array region and the peripheral region;
blanketly depositing a dielectric layer (Upper interconnect dielectric layer; 110; Fig 12; ¶[0072]) over the memory array region and the peripheral region, wherein the dielectric layer covers the memory structure;
performing a reverse etching process (Photolithography/etching process; Figs 13-15; ¶[0075]) to remove a portion (Portions with remaining openings 1502; Fig 15) of the dielectric layer from the memory array region, thereby forming an upwardly protruding wall structure (Outer portions of dielectric layer 110 on sides of openings 1502; Fig 15) along a perimeter of the memory array region,
wherein a thickness of the dielectric layer within the memory array region increases from a central area (Center of openings 1502; Fig 15) of the memory array region to the perimeter (Outer portions of dielectric layer 110; Fig 15) of the memory array region; and
Chen, Figs 13-15: Performing an etching process of dielectric layer above memory array and peripheral regions
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subjecting the dielectric layer to a polishing process (CMP process; ¶[0077]) to remove the upwardly protruding wall structure from the memory array region.
Re Claim 2, (Original) Chen teaches the method according to claim 1, wherein the dielectric layer (Upper interconnect dielectric layer; 110; Fig 12; ¶[0072]) comprises a low-k or ultra-low k dielectric material layer (ELK, i.e. extra low-k; ¶[0025]).
Re Claim 3, (Original) Chen teaches the method according to claim 1, wherein before performing the reverse etching process (Photolithography/etching process; Figs 13-15; ¶[0075]),
the dielectric layer (Upper interconnect dielectric layer; 110; Fig 12; ¶[0072]) has a top surface within the memory array region (Memory region; 502; Fig 12; ¶[0054]) that is higher than a top surface of the dielectric layer within the peripheral region (Peripheral region; 506; Fig 12; ¶[0054]) (Top surface of dielectric layer 110 within memory region 502 is higher than top surface of 110 over peripheral region 506).
Re Claim 5, (Original) Chen teaches the method according to claim 1, wherein the memory structure comprises a conductive via (Bottom electrode vias; BV; Fig 12; ¶[0026]) embedded in a first intermediate dielectric layer (Via dielectric layer; 114; Fig 12; ¶[0026]), a memory storage structure (Memory cell structures; 102a/102b; Fig 12; ¶[0033]) embedded in a second intermediate dielectric layer (Inter-cell filler layer; 108; Fig 12; ¶[0032]), and
a protective layer (Dielectric liner; 218; Fig 12; ¶[0036]) covering a sidewall (Sidewalls of 102a/102b) of the memory storage structure and the first intermediate dielectric layer (Dielectric liner 218 also covers via dielectric layer 114; Fig 12).
Re Claim 6, (Original) Chen teaches the method according to claim 5, wherein the memory storage structure (Memory cell structures; 102a/102b; Fig 12; ¶[0033]) comprises a magnetic tunneling junction (MTJ) structure (Data storage elements/electrodes; 202/204/206; Fig 12; ¶[0034]) situated directly on the conductive via (Bottom electrode vias; BV; Fig 12; ¶[0026]).
Re Claim 7, (Original) Chen teaches the method according to claim 5, wherein the conductive via (Bottom electrode vias; BV; Fig 8/12; ¶[0026]) comprises a tungsten via (Bottom via bodies 214, i.e. a component of vias BV comprises Tungsten; Fig 8; ¶[0035]).
Re Claim 8, (Original) Chen teaches the method according to claim 5, wherein the first intermediate dielectric layer (Via dielectric layer; 114; Fig 12; ¶[0026]) extends into the peripheral region (Peripheral region; 506; Fig 12; ¶[0054]).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Hsia-Wei et al. (Pub No. US 20200127053 A1) (hereinafter, Chen) as applied to claims 1 and 8 above, and further in view of Shen, Hsiang-Ku et al. (Pub No. US 20220165940 A1) (hereinafter, Shen).
Re Claim 4, (Original) Chen does not teach the method according to claim 1, wherein after subjecting the dielectric layer to the polishing process, a remaining thickness of the dielectric layer within the memory array region is 500-800 angstroms.
However, the ordinary artisan would have recognized the thickness of the dielectric layer within the memory array region in a range of 500 to 800 angstroms, to be a result effective variable affecting the conduction between the memory storage structure and magnetic tunneling junction and the electrical isolation provided by the dielectric layer. Thus, it would have been obvious to modify the thickness of the dielectric layer within the memory array region within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. (See MPEP 2144.05 II.B)
Re Claim 9, (Original) Chen does not teach the method according to claim 8, wherein the dielectric layer is in direct contactwith the first intermediate dielectric layer within the peripheral region.
In the same field of endeavor, Shen teaches the method according to claim 8, wherein the dielectric layer (Dielectric layer; 258; Fig 3O; ¶[0020]) is in direct contact with the first intermediate dielectric layer (Dielectric barrier layer; 210; Fig 3O; ¶[0020]) within the peripheral region (Logic region; 100B; Fig 3O; ¶[0014]).
Shen, Fig 3O: MRAM device with dielectric layer directly contacting intermediate dielectric layer
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used the dielectric layer in direct contact with the first intermediate dielectric layer within the peripheral region, as taught by Shen, for the semiconductor structure of Chen. One would have been motivated to do this with a reasonable expectation of success because it is more cost effective and conserves materials to use a uniform first intermediate dielectric layer spanning both the memory array region and peripheral region before depositing the dielectric layer over the intermediate dielectric layer.
Allowable Subject Matter
11. Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 10, the closest prior art Chen, Hsia-Wei et al. (Pub No. US 20200127053 A1) (hereinafter, Chen) either singularly or in combination fails to anticipate or render obvious
“The method according to claim 1 further comprising:
subjecting the upwardly protruding wall structure to an etching process to form through channels in the upwardly protruding wall structure,
thereby dividing the upwardly protruding wall structure into a plurality of islands disposed along the perimeter of the memory array region,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, re claim 10, Chen does not disclose etching channels in the upwardly protruding wall structure along the perimeter of the memory array region. Instead, referring to Figures 12-15, Chen etches the dielectric material 110 to create openings on which an upwardly protruding wall structure is disposed on the sides of said openings. Therefore, claim 10 is found allowable because the prior art does not comprise of essential elements required yield a predictable result.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Kao, Hsiang-Lun et al. (Pub No. US 20230138005 A1) discloses an MRAM structure for improving process control which comprises of magnetic tunnel junction layers and data storage elements within a memory array region and a peripheral region for input/output connections.
[2] Lin, Han-Ting et al. (Pub No. US 20220271087 A1) discloses an MRAM structure comprising of MJT and data storage elements within an array region comprising of MRAM cells stacked on a substrate, combined with a logic region where logic circuits are formed.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
/T.E.D./
Examiner
Art Unit 2817
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