DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 3, 6, 7, 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al. (7883991).
With regard to claim 1, Wu et al. disclose a method for processing a semiconductor substrate (for example, see figs. 2A – 2E), the method comprising:
receiving the semiconductor substrate (200, fig. 2A), the semiconductor substrate (200, fig. 2A) having a frontside surface (200b, fig. 2A), a backside surface (200a, fig. 2A), a side edge surface (referred to as “200c” by examiner’s annotation shown in fig. 2A below), a peripheral edge region (referred to as “P1” by examiner’s annotation shown in fig. 2A below) and a frontside center region (referred to as “C1” by examiner’s annotation shown in fig. 2A below) adjacent to the side edge surface (200c),
wherein the peripheral edge region (P1) includes the side edge surface (200c) and annular portions (referred to as “200c1” by examiner’s annotation shown in fig. 2A below) of the frontside surface (200b) and an annular portion (referred to as “200c1” by examiner’s annotation shown in fig. 2B below) of the backside surface (200a) adjacent to the side edge surface (200c), and
wherein the frontside center region comprises active circuit components (400, fig. 2E) and extends from a center of frontside surface (a middle region surface of the frontside center region) to the peripheral edge region;
spin-on depositing a sacrificial film (coating an adhesive layer 202, applied in spin-on method, inherently functioning as a spin-on depositing a sacrificial film in order to remove a top portion of the substrate 200 as shown in fig. 2C; for example, see column 2, lines 61 - 67) within the peripheral edge region (P1) of the semiconductor substrate (200), and not within the frontside center region (C1, fig. 2A) wherein said spin-on depositing the sacrificial film (202) uses a spin-on deposition process (for example, see column 2, lines 61 - 67) to coat the peripheral edge region (P1) with the sacrificial film (202), including the side edge surface (200c, fig. 2B), the annular portion (200c1 as shown in fig. 2B) of the frontside surface and annular portion (200c1 as shown in fig. 2B) of the backside surface of the semiconductor substrate (200); and
processing the semiconductor substrate (200) after spin-on depositing the sacrificial film (202), wherein said processing comprises:
etching (as shown in figs. 2B, 2C) an exposed surface (a top surface functioning as an exposed surface) of at least one material layer (referred to as “C1” by examiner’s annotation shown in fig. 2B below) provided within the frontside center region (C1) of the semiconductor substrate (200),
wherein the sacrificial film (202) inherently protects the peripheral edge region (P1) of the semiconductor substrate (200) from damage during said etching (the etching, as shown in figs. 2B, 2C, the exposed surface of at least one material layer C1 shown in fig. 2B below).
PNG
media_image1.png
442
688
media_image1.png
Greyscale
PNG
media_image2.png
352
612
media_image2.png
Greyscale
PNG
media_image3.png
336
589
media_image3.png
Greyscale
With regard to claim 2, Wu et al. disclose said spin-on depositing the sacrificial film (202) comprises dispensing a liquid material (for example, see column 3, lines 2 – 6) within the peripheral edge region (P1) that is not removed during said processing (because the sacrificial film 202, fig. 2C still formed on the peripheral edge region P1 as shown in fig. 2C)
With regard to claim 3, Wu et al. disclose dispensing the liquid material (for example, see column 3, lines 2 – 6) comprises dispensing a spin-on glass material (spin-on dielectric material 202 inherently including a spin-on glass material; for example, see column 2, lines 61 - 67)) within the peripheral edge region (P1) of the semiconductor substrate (200).
With regard to claim 6, Wu et al. disclose said spin-on depositing the sacrificial film comprises dispensing the liquid material (for example, see column 3, lines 2 – 6) comprises dispensing a spin-on glass material (spin-on dielectric material 202 inherently including a spin-on glass material; for example, see column 2, lines 61 - 67)) within the peripheral edge region (P1) of the semiconductor substrate (200) and on the backside surface (200a) of the semiconductor substrate (200).
With regard to claim 7, Wu et al. disclose the dispensing the liquid material (for example, see column 3, lines 2 – 6) comprises dispensing a spin-on glass material (spin-on dielectric material 202 inherently including a spin-on glass material; for example, see column 2, lines 61 - 67)) within the peripheral edge region (P1) of the semiconductor substrate (200) and on the backside surface (200a) of the semiconductor substrate (200).
With regard to claim 9, Wu et al. disclose said processing the semiconductor substrate comprises: providing the semiconductor substrate (200) within a processing chamber (the layer 202 having a trench functioning as a processing chamber) having a chuck (a carrier 300, fig. 2B) configured to support one or more surfaces of the semiconductor substrate (200); and wherein the sacrificial film (202) inherently protects the peripheral edge region (P1) and/or the backside surface (200a) of the semiconductor substrate (200) from damage caused by the chuck (300).
Allowable Subject Matter
3. Claims 4, 5, 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4 is allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as said dispensing the liquid material is performed within a processing chamber comprising a frontside bevel nozzle, and wherein said dispensing the liquid material comprises: using the frontside bevel nozzle to dispense the liquid material onto the annular portion of the frontside surface while spinning the semiconductor substrate at a rotational speed, which causes the liquid material to wrap around the side edge surface of the semiconductor substrate to coat the annular portion of the backside surface as recited in claim 4.
Claim 5 is allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as said dispensing the liquid material is performed within a processing chamber comprising a backside bevel nozzle, and wherein said dispensing the liquid material comprises: using the backside bevel nozzle to dispense the liquid material onto the annular portion of the backside surface while spinning the semiconductor substrate at a rotational speed, which causes the liquid material to wrap around the side edge surface of the semiconductor substrate to coat the annular portion of the frontside surface as recited in claim 5.
Claim 8 is allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as said dispensing the liquid material is performed within a processing chamber comprising a backside nozzle, and wherein said dispensing the material comprises: using the backside nozzle to dispense the liquid material onto the backside surface of the semiconductor substrate near the center of the semiconductor substrate while spinning the semiconductor substrate at a rotational speed, which causes the liquid material to cover the backside surface and wrap around the side edge surface of the semiconductor substrate to coat the annular portion of the frontside surface as recited in claim 8.
Claims 10 – 14 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as said processing the semiconductor substrate comprises: etching the exposed surface of the at least one material layer provided within the frontside center region of the semiconductor substrate using a wet or dry etch process, which exposes the frontside center region and the peripheral edge region of the semiconductor substrate to an etchant chemical or gas; and wherein the sacrificial film acts as a hard mask to protect the peripheral edge region of the semiconductor substrate from being etched by the etchant chemical or gas during the wet or dry etch process as recited in claim 10.
Claims 15 – 20 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as said processing the semiconductor substrate comprises: depositing the at least one material layer within the frontside center region of the semiconductor substrate using a dry deposition process, which exposes the frontside center region and the peripheral edge region of the semiconductor substrate to a process gas; and wherein the sacrificial film protects the peripheral edge region of the semiconductor substrate from gas particles that adhere to the sacrificial film during the dry deposition process as recited in claim 15.
Response to Arguments
Applicant’s arguments filed 04/23/26 have been fully considered but they are not persuasive.
It is argued, at page of the remarks, that “Wu fails to provide anticipatory teaching for spin-on depositing a sacrificial film within a peripheral edge region, and not within a frontside center region, of a semiconductor substrate”. However, fig. 2A of Tsai et al. does show spin-on depositing a sacrificial film (coating an adhesive layer 202, applied in spin-on method, inherently functioning as a spin-on depositing a sacrificial film in order to remove a top portion of the substrate 200 as shown in fig. 2C; for example, see column 2, lines 61 - 67) within the peripheral edge region (P1) of the semiconductor substrate (200), and not within the frontside center region (C1, fig. 2A).
PNG
media_image1.png
442
688
media_image1.png
Greyscale
It is argued, at page of the remarks, that “Wu fails to provide anticipatory teaching for spin-on depositing a sacrificial film within a peripheral edge region, which includes the side edge surface, the annular portion of the frontside surface and the annular portion of the backside surface of the semiconductor substrate”. However, fig. 2B of Tsai et al. do show the spin-on depositing the sacrificial film (202) uses a spin-on deposition process (for example, see column 2, lines 61 - 67) to coat the peripheral edge region (P1) with the sacrificial film (202), including the side edge surface (200c, fig. 2B), the annular portion (200c1 as shown in fig. 2B) of the frontside surface and annular portion (200c1 as shown in fig. 2B) of the backside surface of the semiconductor substrate (200).
PNG
media_image2.png
352
612
media_image2.png
Greyscale
Conclusion
7. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights