DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the amendment filed 7/9/2026 in which claims 1, 13, 18, 25, 36, and 39 were amended and claim 41 was added.
Claims 1-10, 13, 18-21, 25, 36, and 38-41 are pending and presented for examination.
Terminal Disclaimer
The terminal disclaimer filed on 7/8/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US Patents 12408403 and 11658234 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 36 and 38-40 are rejected under 35 U.S.C. 103 as being unpatentable over Akiyama et al (US 2013/0193485 and Akiyama hereinafter) in view of Wu et al (US 2009/0267116 and Wu hereinafter).
As to claims 36 and 38-40: Akiyama discloses [claim 36] a transistor device (Fig. 13), comprising: a semiconductor structure (comprising 101, 102, 103, and 104; [0038]) including a channel layer (103; [0038]) and a barrier layer (104; [0038]) on the channel layer (103), wherein the barrier layer (104) has a higher bandgap than the channel layer ([0038]); a source contact (112s; [0038]) and a drain contact (112d; [0038]) on the barrier layer (104); a gate contact (108g; [0038]) on the semiconductor structure (comprising 101, 102, 103, and 104) between the source contact (112s) and the drain contact (112d); and a field plate (121; [0064]) on the semiconductor structure (comprising 101, 102, 103, and 104) between the gate contact (108g) and the drain contact (112d) and laterally offset (gap in which 109 is filled) from the gate contact (108g) by a distance (gap in which 109 is filled), the field plate (121) including a source-side wing portion (121 has two wing portions, both on top of the top surface of 132, one extending toward the drain 112d and one extending toward the source 112s) extending from a central portion (portion of 121 in opening 107b; [0073]) of the field plate (121); [claim 38] wherein the field plate (121) further includes a drain-side wing portion (the drain-side wing portion is interpreted to be the wing portion extending toward 112d) extending from the central portion (portion of 121 in opening 107b; [0073]) of the field plate (121); [claim 39] wherein the gate contact (108g) includes a drain-side wing portion (gate 108g has two wing portions, both on top of the top surface of 132, one extending toward the drain 112d and one extending toward the source 112s) extending from a central portion (portion of 108g in opening 133; [0073]) of the gate contact (108g); [claim 40] wherein the gate contact (108g) further includes a source-side wing portion (gate 108g has two wing portions, both on top of the top surface of 132, one extending toward the drain 112d and one extending toward the source 112s) extending from the central portion (portion of 108g in opening 133) of the gate contact (108g).
Akiyama fails to expressly disclose [claim 36] wherein the source-side wing portion of the field plate is laterally offset from the gate contact by a distance between about 0.3 μm and 0.5 μm; [claim 39] where the drain-side wing portion of the gate contact is laterally offset from the source-side wing portion of the field plate by the distance.
Wu discloses in Fig. 2 a field plate 30 that is in the same location (between the gate and the drain) as field plate 121 of Akiyama. Wu discloses where the left-most vertical edge (the source-side) of field plate 30 is spaced apart from the right-most vertical edge (the drain-side) of the gate electrode 24 by a distance Lgf, where Lgf should be equal to or less than 0.4 μm, see [0041].
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to choose the distance between adjacent edges of the gate electrode and field plate (such as the right-most edge of the gate electrode in Akiyama, which is the drain-side wing portion’s edge and the left-most edge of the field plate in Akiyama, which is the source-side wing portion’s edge) such that the distance is within the claimed range, as taught by the Wu where the same adjacent edges as mentioned in Akiyama are spaced by the distance, in order to provide enough isolation from the field plate while being small enough to maximize the field effect provided by the field plate ([0041]).
Allowable Subject Matter
Claims 1-10, 13, 18-21, and 25 are allowed over the prior art of record.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 1: the closest prior art, Akiyama, discloses a transistor device (Fig. 13), comprising: a semiconductor structure (comprising 101, 102, 103, and 104; [0038]) including a channel layer (103; [0038]) and a barrier layer (104; [0038]) on the channel layer (103), wherein the barrier layer (104) has a higher bandgap than the channel layer ([0038]); a source contact (112s; [0038]) and a drain contact (112d; [0038]) on the barrier layer (104); a gate contact (108g; [0038]) on the semiconductor structure (comprising 101, 102, 103, and 104) between the source contact (112s) and the drain contact (112d); and a field plate (121; [0064]) on the semiconductor structure (comprising 101, 102, 103, and 104) between the gate contact (108g) and the drain contact (112d) and laterally offset (gap in which 109 is filled) from the gate contact (108g) by a distance (gap in which 109 is filled), the field plate (121) including a first wing portion (121 has two wing portions, both on top of the top surface of 132, one extending toward the drain 112d and one extending toward the source 112s) extending from a central portion (portion of 121 in opening 107b; [0073]) of the field plate (121). Akiyama fails to expressly disclose wherein the transistor device exhibits a minimum noise figure (Fmin) that is less than 3.4 across a range of operating frequencies, wherein the range comprises frequencies of 10GHz and higher.
As to claim 18: the closest prior art, Akiyama, discloses a transistor device (Fig. 13), comprising: a semiconductor structure (comprising 101, 102, 103, and 104; [0038]) including a channel layer (103; [0038]) and a barrier layer (104; [0038]) on the channel layer (103), wherein the barrier layer (104) has a higher bandgap than the channel layer ([0038]); a source contact (112s; [0038]) and a drain contact (112d; [0038]) on the barrier layer (104); a gate contact (108g; [0038]) on the semiconductor structure (comprising 101, 102, 103, and 104) between the source contact (112s) and the drain contact (112d); and a field plate (121; [0064]) on the semiconductor structure (comprising 101, 102, 103, and 104) between the gate contact (108g) and the drain contact (112d) and laterally spaced apart (gap in which 109 is filled) from the gate contact (108g) by a distance (gap in which 109 is filled). Akiyama fails to expressly disclose wherein the transistor device exhibits a minimum noise figure (Fmin) that is less than 3.4 across a range of operating frequencies from 0.3 GHz to 26 GHz, inclusive.
Claim 41 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Regarding claims 1-10, 13, 18-21, and 25: applicant’s arguments, see pages 10 and 11, filed 7/9/2026, with respect to the Fisher reference's narrow range compared to the claimed range have been fully considered and are persuasive. The 103 rejection of claim 18 made in the Office action mailed 4/10/2026 has been withdrawn.
Regarding claims 36 and 38-40: applicant's arguments filed 7/9/2026 have been fully considered but they are not persuasive.
In the remarks, applicant argues in substance that Wu does not disclose or suggest the use of the claimed spacing with a field plate configuration including “a source-side wing portion extending from a central portion of the field plate” as required by claim 1. Wu describes field plates with source-side wing portions 62, 112, 146, and 166, all of which overlap the gate 24. While Wu may disclose that the spacing Lgf between gate 24 and field plate 30 as 0.4 microns or less, Wu specifically notes that ranges for the spacing Lgf are not required for field plates with gate portions, which are shown to be overlapping the gate 24. Even if Wu is used to modify Akiyama, paragraph 0138 of the specification establishes the criticality of the claimed lateral offset between the field plate and the gate contact in achieving unexpected results of a lower noise figure over a wide operating frequency range which may not be achieved in other field plates including source-side wing portions.
Examiner respectfully traverses applicant’s remarks. Examiner notes that Wu does not describe any of the field plates 62, 112, 146, and 166 as having wing portions and 30 not having wing portions. Examiner interprets a wing portion in Wu to be a section of the field plate that extends from a line running from the center of the field plate in a source or drain direction. Therefore, 30 has a “wing” portion (which is the left half of 30) and the left-most edge of 30 is spaced from the right-most edge of the gate 24 (the gate drain-side “wing” portion) by the distance of 0.4 microns or less. The field plate 30 in Fig. 2 of Wu is in the same location and is spaced apart from the gate electrode 24 as desired in Akiyama. The other embodiments of Wu mentioned by applicant do not correspond to the field plate of Akiyama as they overlap the gate, which is not desired by Akiyama. Further, to overcome a prima facie case of obviousness with respect to optimization of ranges, unexpected results must be shown relative to the range taught by the prior art, see MPEP 716.02(e). The evidence should establish that the differences in results are in fact unexpected and unobvious and of both statistical and practical significance, as stated in MPEP 716.02(b). The sections of the specification do not establish criticality or unexpected results as the benefits “may” reduce the input capacitance. Wu discloses ranges that overlap with the claimed range and provides a reason to modify Akiyama to perform such a modification, as noted in the rejection. The claims also do not recite that the distance affects the noise figure nor does it claim anything about the noise figure. As stated in MPEP 71.02(d), the objective evidence of nonobviousness must be commensurate in scoped with the claims which the evidence is offered to support.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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