Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II, Species I in the reply filed on May 20, 2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21, 27, and 32-34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 21, it is unclear whether it is just the combination of the first and second capping layers that must have greater thickness than the TFR layer or if each of the two layers must individually have a greater thickness than the TFR layer. For the purposes of examination, the claim is being interpreted such that each of the two capping layers individually must have a thickness greater than the TFR layer.
Regarding claim 27, it is unclear what exactly is meant by the phrase “more quickly” as it is unclear if this means a difference in the time spent etching each layer during the process or if it is a difference in the etching rate of each layer during the process. For the purposes of examination, the claim is being interpreted to mean that the first and second capping layers have a different etching rate during the process such that the etching rate of the second capping layer is greater than the etching rate of the first capping layer during the first etch process.
Regarding claims 32, 33, and 34, it is unclear what part of the device the “second dielectric layer” is in reference to as in light of the specification it appears these claims are in reference to the etch stop layer 110 and not the second dielectric layer 214b. As the specification does not seem to teach the limitations of these claims with respect to the second dielectric layer 214b, but it does seem teach them with respect to the etch stop layer 110. Also claim 30 refers to “a second dielectric layer” and that does appear to be in reference to the second dielectric layer 214b of the specification. Therefore, there is a mixing of terminology between claims and the specification that is rendering 32, 33, and 34 claims indefinite as the meaning of every term should be apparent (MPEP 2173.05(a)). For the purposes of examination, the “second dielectric layer” of claims 32, 33, and 34 is being interpreted to in reference to the etch stop layer 110 taught by the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 16, 20, 32, and 33 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Jerome et al. (Pub. No. US 20220271118 A1), hereinafter referred to as Jerome.
Regarding claim 16, Jerome teaches a method of forming an integrated chip, comprising: forming a thin film resistor (TFR) layer over a semiconductor substrate (Fig. 14A, SiCr thin film 15tf, semiconductor substrate 100s; ¶68-71); forming a capping structure over a middle region of the TFR layer (Figs 14A & 14B, Oxide layer 17, SiCr thin film 15tf; ¶68-72); depositing a conductive layer and an etch stop layer over the TFR layer and the capping structure (Fig. 14C, TiN layer 30, SiON layer 31; ¶68-73); and performing a first patterning process on the conductive layer and the etch stop layer, thereby defining a pair of conductive structures on outer regions of the TFR layer, wherein the capping structure is disposed on the TFR layer during the first patterning process (Figs. 14D & 14E, contact pads 30cp, oxide layer 17, SiCr resistor 15; ¶68-75).
Regarding claim 20, Jerome further teaches depositing an upper dielectric layer over the TFR layer, wherein the upper dielectric layer contacts outer sidewalls of the TFR layer, and wherein the capping structure is disposed directly between a lower surface of the upper dielectric layer and a top surface of the TFR layer (Fig. 14F, Second interlayer dielectric layer (ILD) 13D2, oxide layer 17; ¶68-77).
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Regarding claim 32, Jerome teaches a method for forming an integrated chip, comprising: forming a thin film resistor (TFR) structure on a first dielectric layer over a semiconductor substrate, wherein the TFR structure comprises a middle region and a pair of outer regions spaced on opposing sides of the middle region, wherein a width of the middle region is less than widths of the outer regions (Figs. 3 & 14A, SiCr thin film 15tf, semiconductor substrate 100s, width wb, width wrh; ¶32-33 and 68-71); forming a capping structure over the middle region of the TFR structure, wherein the capping structure is laterally offset from outer regions of the TFR structure (Figs. 14A & 14B, Oxide layer 17, SiCr thin film 15tf; ¶68-72); depositing a conductive layer over the capping structure and TFR structure, wherein the conductive layer contacts top surfaces of the outer regions (Fig. 14C, TiN layer 30; ¶68-73); depositing a second dielectric layer on the conductive layer (Fig. 14C, SiON layer 31; ¶68-73); and etching the conductive layer and the second dielectric layer to from a pair of conductive structures on the outer regions, wherein the conductive structures are laterally spaced from one another by the capping structure, wherein a bottom surface of the capping structure is aligned with bottom surfaces of the conductive structures (Figs. 14D & 14E, contact pads 30cp, oxide layer 17, SiCr resistor 15; ¶68-75).
Regarding claim 33, Jerome further teaches a thickness of the second dielectric layer is less than thicknesses of the conductive structures and is greater than a thickness of the capping structure (SiON layer 31, TiN layer 30, oxide layer 17; ¶70 & 73).
Claim(s) 25-27 and 29-31 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Dirnecker et al. (Pub No. US 20180019297 A1), hereinafter referred to as Dirnecker.
Regarding claim 25, Dirnecker teaches a method of forming an integrated chip, comprising: depositing a thin film resistor (TFR) material on a first dielectric layer overlying a semiconductor substrate (Fig. 2A, lower dielectric layer 102, higher sheet resistance material 138; ¶22-25); depositing a first capping layer on the TFR material (Fig. 2B, protective dielectric layer 118; ¶22-26); depositing a second capping layer on the first capping layer (Fig. 2C, intermediate dielectric layer 120; ¶22-28); performing a first etching process on the TFR material to form a TFR structure having a middle region between a pair of outer regions (Figs. 2B & 2C, higher sheet etch process 144, body region 114, head regions 116; ¶22-28); performing a second etching process to remove peripheral portions of the first capping layer and the second capping layer from over the outer regions of the TFR structure, thereby forming a capping structure on the middle region of the TFR structure (Figs. 2D & 2E, first intermediate via etch process 148, second intermediate via etch process 150; ¶22-30); forming a pair of conductive structures over the outer regions of the TFR structure, wherein the pair of conductive structures are formed after the second etching process (Figs. 2G-2J, upper head layers 122; ¶22-37).
Regarding claim 26, Dirnecker further teaches the second etching process comprises performing a first etch on the second capping layer and a second etch on the first capping layer, wherein the first etch stops on the second capping layer, and wherein the first etch is different from the second etch (Figs. 2D & 2E, first intermediate via etch process 148, second intermediate via etch process 150; ¶22-30).
Regarding claim 27, Dirnecker further teaches the second capping layer is etched more quickly than the first capping layer during the first etch (Fig. 2D, first intermediate via etch process 148; ¶22-29).
Regarding claim 29, Dirnecker further teaches a first conductive structure of the pair of conductive structures comprises a vertical segment abutting the capping structure and a lateral segment extending from the vertical segment in a direction away from the capping structure, wherein a length of the vertical segment is less than a length of the lateral segment (Fig. 2J, upper head layers 122; ¶22-37).
Regarding claim 30, Dirnecker further teaches depositing a second dielectric layer over the pair of conductive structures and the capping structure (Fig. 2K, ILD layer 134, upper head layers 122, protective dielectric layer 118, intermediate dielectric layer 120; ¶22-39); and forming a conductive via in the second dielectric layer, wherein the conductive via contacts the lateral segment and is laterally offset from the vertical segment (Fig 2L-2M, ILD layer 134, via holes 166, layer of via liner metal 168, layer of via fill material 170, vias 136; ¶22-44).
Regarding claim 31, Dirnecker further teaches a thickness of the lateral segment is greater than a thickness of the capping structure (upper head layers 122, protective dielectric layer 118, intermediate dielectric layer 120; ¶19-20, 30).
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452
801
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jerome in view of Ito et al. (Pub. No. US 20020115299 A1), hereinafter referred to as Ito.
Regarding claim 17, Jerome teaches the method of claim 16 and further teaches the first patterning process including performing an etch on the conductive layer and the etch stop layer, wherein the etch removes the portion of the conductive layer over the middle region of the TFR layer (Fig. 14D, contact pads 30cp; ¶68-74). However, Jerome does not explicitly teach the first patterning process including performing a first etch and second etch on the conductive layer.
Ito teaches a patterning process including performing a first etch on the conductive layer and the etch stop layer, wherein the first etch reduces a thickness of a portion of the conductive layer over the middle region of the TFR layer (Fig. 5E, barrier metal 4; ¶43-53); and performing a second etch on the conductive layer to remove the portion of the conductive layer over the middle region of the TFR layer, wherein the first etch is different from the second etch (Fig. 5F, barrier metal 4; ¶43-53).
Jerome and Ito are analogous art as they are in the same field of endeavor of thin film resistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerome with the teachings of Ito to have a two stage dry and wet etch patterning process for the conductive layer. For the purpose of having better control over the side etching, as recognized by Ito.
Regarding claim 18, Jerome does not teach the first etch being a dry etch and the second etch being a wet etch.
Ito teaches the first etch being a dry etch and the second etch being a wet etch (Figs. 5E & 5F, barrier metal 4; ¶43-53).
Jerome and Ito are analogous art as they are in the same field of endeavor of thin film resistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerome with the teachings of Ito to have a two stage dry and wet etch patterning process for the conductive layer. For the purpose of having better control over the side etching, as recognized by Ito.
Claim(s) 19, 22-24 and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jerome in view of Dirnecker.
Regarding claim 19, Jerome teaches the method of claim 16 and further teaches depositing a capping layer on the TFR layer (Figs. 14A&14B, oxide layer 17, SiCr thin film 15tf; ¶68-72). However, Jerome does not explicitly teach forming the capping structure including depositing a first capping layer and a second capping layer on the TFR layer; performing a dry etch on the second capping layer; and performing a wet etch on the first capping layer, wherein a first etching rate of the first capping layer is greater than a second etching rate of the TFR layer during the wet etch.
Dirnecker teaches forming the capping structure including depositing a first capping layer and a second capping layer on the TFR layer (Figs. 2A-2C, protective dielectric layer 118, intermediate dielectric layer 120; ¶22-28); performing a dry etch on the second capping layer (Fig. 2D, first intermediate via etch process 148, intermediate dielectric layer 120; ¶22-29); and performing a wet etch on the first capping layer, wherein a first etching rate of the first capping layer is greater than a second etching rate of the TFR layer during the wet etch (Fig. 2E, second intermediate via etch process 150, protective dielectric layer 118, higher sheet layer 112; ¶22-30).
Jerome and Dirnecker are analogous art as they are in the same field of endeavor of thin film resistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Jerome with the method of Dirnecker such that forming the capping structure includes depositing a first capping layer and a second capping layer on the TFR layer; performing a dry etch on the second capping layer; and performing a wet etch on the first capping layer, wherein a first etching rate of the first capping layer is greater than a second etching rate of the TFR layer during the wet etch. For the purpose of having better protection of the TFR layer and to minimize the undercut between the capping layers, as recognized by Dirnecker.
Regarding claim 22, Jerome further teaches the capping structure contacting a first sidewall of a first conductive structure of the pair of conductive structures (Fig. 14E, oxide layer 17, contact pads 30cp; ¶68-75). However, Jerome does not explicitly teach the first sidewall comprising a curved segment over a straight segment, wherein a height of the curved segment is greater than a height of the straight segment.
Dirnecker teaches the capping structure contacting a first sidewall of a first conductive structure of the pair of conductive structures, wherein the first sidewall comprises a curved segment over a straight segment, wherein a height of the curved segment is greater than a height of the straight segment (Fig. 2J, protective dielectric layer 118, intermediate dielectric layer 120, upper head layer 122; ¶19-37).
Jerome and Dirnecker are analogous art as they are in the same field of endeavor of thin film resistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Jerome with the teachings of Dirnecker such that the first sidewall comprises a curved segment over a straight segment, wherein a height of the curved segment is greater than a height of the straight segment. For the purpose of conformally forming the conductive layer over the capping layer.
Regarding claim 23, Jerome does not teach the first conductive structure comprising a second sidewall laterally offset from the capping structure, wherein the second sidewall is curved and has a height greater than a thickness of the capping structure.
Dirnecker teaches the first conductive structure comprising a second sidewall laterally offset from the capping structure, wherein the second sidewall is curved and has a height greater than a thickness of the capping structure (Fig. 2J, protective dielectric layer 118, intermediate dielectric layer 120, upper head layer 122; ¶19-37).
Jerome and Dirnecker are analogous art as they are in the same field of endeavor of thin film resistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Jerome with the teachings of Dirnecker such that the first conductive structure comprises a second sidewall laterally offset from the capping structure, wherein the second sidewall is curved and has a height greater than a thickness of the capping structure. For the purpose of conformally forming the conductive layer over the capping layer.
Regarding claim 24, Jerome does not teach the height of the straight segment is equal to a thickness of the capping structure.
Dirnecker teaches the height of the straight segment is equal to a thickness of the capping structure (Fig. 2J, protective dielectric layer 118, intermediate dielectric layer 120, upper head layer 122; ¶19-37).
Jerome and Dirnecker are analogous art as they are in the same field of endeavor of thin film resistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Jerome with the teachings of Dirnecker such that the height of the straight segment is equal to a thickness of the capping structure. For the purpose of simplifying the manufacturing process and saving on manufacturing costs by reducing the amount of material used.
Regarding claim 34, Jerome teaches the method of claim 33 and further teaches the capping structure comprising a first dielectric capping layer on the TFR structure, wherein the material of the first dielectric capping layer is a different material of the second dielectric layer. (Figs. 14A-14C, oxide layer 17, SiON layer 31; ¶68-73). However, Jerome does not explicitly teach the capping structure having a second dielectric capping layer on the first dielectric capping layer, wherein the material of the second dielectric capping layer is a different material of the second dielectric layer.
Dirnecker teaches the capping structure comprises a first dielectric capping layer on the TRF structure and a second dielectric capping layer on the first dielectric capping layer (Figs. 2B&2C, protective dielectric layer 118, intermediate dielectric layer 120; ¶22-28), wherein materials of the first and second dielectric capping layers are different from a material of the second dielectric layer (Figs. 2B, 2C, & 2J, protective dielectric layer 118, intermediate dielectric layer 120, hard mask 126; ¶19, 22-37).
Jerome and Dirnecker are analogous art as they are in the same field of endeavor of thin film resistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Jerome with the method of Dirnecker such that comprises a first dielectric capping layer on the TRF structure and a second dielectric capping layer on the first dielectric capping layer, wherein materials of the first and second dielectric capping layers are different from a material of the second dielectric layer. For the purpose of better protecting the TFR layer and having the second dielectric layer act as an etch stop and/or mask during etching processes.
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dirnecker in view of Jerome.
Regarding claim 28, Dirnecker teaches the method of claim 25 and further teaches the capping structure extending between the pair of conductive structures along a first direction (). However, Dirnecker does not teach explicitly teach a width of the capping structure along a second direction being less than a width of the outer regions of the TFR structure, wherein the second direction is substantially orthogonal to the first direction.
Jerome teaches the capping structure extending between the pair of conductive structures along a first direction, wherein a width of the capping structure along a second direction is less than a width of the outer regions of the TFR structure, wherein the second direction is substantially orthogonal to the first direction (Figs. 3, 12, and 14F, oxide layer 17, contact pads 30cp, resistor head portions 15RH, width wrh, resistor body 15B, width wb; ¶32-33, 59-62, 68-79).
Dirnecker and Jerome are analogous art as they are in the same field of endeavor of thin film resistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Dirnecker with the teachings of Jerome such that the capping structure extends between the pair of conductive structures along a first direction, wherein a width of the capping structure along a second direction is less than a width of the outer regions of the TFR structure, wherein the second direction is substantially orthogonal to the first direction. For the purpose of having the capping structure conform to the shape of the body of the TFR to better protect the TFR layer and reduce manufacturing cost by using only the necessary amount of material.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jerome in view of Dirnecker as applied to claim 19 above, and further in view of Hiroshima (US Patent No. 10,446,295 B2).
Regarding claim 21, Jerome does not teach a thickness of the first capping layer and a thickness of the second capping layer being greater than a thickness of the TFR layer.
Hiroshima teaches a thickness of the first capping layer and a thickness of the second capping layer being greater than a thickness of the TFR layer (thin-film resistive pattern 3a, first protective film 11, second protective film 12; ¶16, 22-60).
Jerome, Dirnecker, and Hiroshima are all analogous art as they are in the same field of endeavor of thin film resistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Jerome in view of Dirnecker with the teachings of Hiroshima such that a thickness of the first capping layer and a thickness of the second capping layer is greater than a thickness of the TFR layer. For the purpose of providing optimal protection of the TFR layer from damage such as moisture, as recognized by Hiroshima.
Claim(s) 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jerome in view of Ito and in further view of Lee (Pub. No. US 20130093055 A1).
Regarding claim 35, Jerome teaches the method of claim 32 and further teaches etching the conductive layer to remove portions of the conductive later laterally offset from the outer regions (Fig. 14D, TiN layer, contact pads 30cp; ¶68-74). However, Jerome does not explicitly teach using a two etch process to remove the conductive layer, wherein the second etch forms curved sidewalls in the conductive structures.
Ito teaches an etching the conductive layer comprises performing a first etch to reduce thicknesses of portions of the conductive layer laterally offset from the outer regions (Fig. 5E, barrier metal 4; ¶43-53); and a second etch to remove the portions of the conductive layer (Fig. 5F, barrier metal 4; ¶43-53).
Jerome and Ito are analogous art as they are in the same field of endeavor of thin film resistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerome with the teachings of Ito to have a two stage dry and wet etch patterning process for the conductive layer. For the purpose of having better control over the side etching, as recognized by Ito.
However, Jerome in view of Ito does not explicitly teach the second etch forming curved sidewalls in the conductive structures.
Lee teaches etching the conductive layer to form curved sidewalls (Fig. 4, metal head layer 400, metal head patterns 410 and 420; ¶20-21, 31).
Jerome, Ito, and Lee are all analogous art as they are in the same field of endeavor of thin film resistors. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerome in view of Ito with the teachings of Lee such that the second etching process forms curved sidewalls in the conductive structures. For the purpose of more easily manufacturing a TFR having a relatively stable resistance, simplifying manufacturing and reducing manufacturing costs, as recognized by Lee.
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./ Examiner, Art Unit 2897
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