Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Species II, claims 1-16 in the reply filed on April 15, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, and 7 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Xie et al. (Pub. No. US 20230420359 A1), hereinafter referred to as Xie.
Regarding claim 1, Xie teaches a semiconductor structure, comprising: a first circuit area having: an active region extending lengthwise along a first direction, the active region includes a channel region between source/drain (S/D) features and a gate over the channel region, a dielectric structure over and surrounding the active region, a metal contact penetrating through a top surface of the dielectric structure to land on one of the S/D features, and a first via landing on the metal contact (Fig. 21D & 23A-23C, NFET, PFET, active semiconductor layers 208, high-k metal gate 210, S/D epitaxial layers 214, ILD layer 216, first contact 260, BEOL 263; ¶105-108); and a second circuit area having: the dielectric structure, a feedthrough via penetrating through the top surface of the dielectric structure and a bottom surface of the dielectric structure, and a second via landing on the feedthrough via, wherein the first via and the second via have substantially coplanar bottom surfaces (Fig. 21D & 23A-23C, ILD layer 216,
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power rail 262, BEOL layer 263; ¶105-108).
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Regarding claim 4, Xie further teaches the feedthrough via continuously and uniformly spanning from the bottom surface of the dielectric structure to at least the top surface of the dielectric structure (Figs. 23B & 23C, power rail 262, ILD layer 216; ¶105-108).
Regarding claim 7, Xie further teaches the bottom and side surfaces of the metal contact is embedded in the dielectric structure, and the bottom surface of the metal contact is below a top surface of the feedthrough via (Fig. 23C, first contact 260, ILD layer 216, power rail 262; ¶105-108).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Su et al. (Pub. No. US 20220344496 A1), hereinafter referred to as Su.
Regarding claim 2, Xie does not explicitly teach the feedthrough via partially penetrates through a bottom surface of the second via.
Su teaches increasing the size of the interface between a via and a source feature in order to lower resistance.
Xie and Su are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Xie to incorporate the teachings of Su to have the feedthrough via partially penetrate through a bottom surface of the second via. For the purpose of creating larger interface between them in order to reduce the resistance of the device.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Su as applied to claim 2 above, and further in view of Rahman et al. (Pub. No. US 20250132245 A1), hereinafter referred to as Rahman.
Xie in view of Su does not explicitly teach the second via including a glue layer and a via fill layer, the glue layer being disposed on side and bottom surfaces of the via fill layer, wherein the feedthrough via completely penetrates through a bottom portion of the glue layer disposed directly on the via fill layer.
Rahman teaches a via and contacts including a glue layer and a via fill layer, the glue layer being disposed on side and bottom surfaces of the via fill layer (S/D contacts 214, deep trench via 226, electrically conductive fill material 314 & 320, interface material 316; ¶48-56).
Xie, Su, and Rahman are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the feedthrough via penetrating the second via of Xie in view of Su to incorporate the glue layer of Rahman such that the second via including a glue layer and a via fill layer, the glue layer being disposed on side and bottom surfaces of the via fill layer, wherein the feedthrough via completely penetrates through a bottom portion of the glue layer disposed directly on the via fill layer. For the purpose of reducing contact resistance, as recognized by Rahman, and/or providing a barrier for the fill material to protect from diffusion into surrounding materials.
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Rahman.
Regarding claim 5, Xie teaches the structure of claim 1. However, it does not explicitly teach the feedthrough via includes a glue layer and a via fill layer, wherein the glue layer is disposed on side and top surfaces of the via fill layer, and the via fill layer is separated from the second via by the glue layer.
Rahman teaches the feedthrough via includes a glue layer and a via fill layer, wherein the glue layer is disposed on side and top surfaces of the via fill layer, and the via fill layer is separated from the second via by the glue layer (deep trench via 226, electrically conductive fill material 320, interface material 316; ¶48-56).
Xie and Rahman are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xie with the glue layer of Rahman such that the feedthrough via includes a glue layer and a via fill layer, wherein the glue layer is disposed on side and top surfaces of the via fill layer, and the via fill layer is separated from the second via by the glue layer. For the purpose of reducing contact resistance, as recognized by Rahman, and/or providing a barrier for the fill material to protect from diffusion into surrounding materials.
Regarding claim 6, Xie teaches the structure of claim 1. However, Xie does not explicitly teach the feedthrough via including a glue layer and a via fill layer, wherein the glue layer is disposed on side surfaces of the via fill layer but not on a top surface of the via fill layer, and the top surface of the via fill layer directly contacts the second via.
Rahman teaches the feedthrough via includes a glue layer and a via fill layer, wherein the glue layer is disposed on side surfaces of the via fill layer but not on a top surface of the via fill layer, and the top surface of the via fill layer directly contacts the second via the feedthrough via includes a glue layer and a via fill layer, wherein the glue layer is disposed on side surfaces of the via fill layer but not on a top surface of the via fill layer, and the top surface of the via fill layer directly contacts the second via (Figs. 4A-4F, deep trench via 226, electrically conductive fill material 320, interface material 316, first interconnect layer 406; ¶48-60).
Xie and Rahman are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xie with the glue layer of Rahman such that the feedthrough via includes a glue layer and a via fill layer, wherein the glue layer is disposed on side surfaces of the via fill layer but not on a top surface of the via fill layer, and the top surface of the via fill layer directly contacts the second via. For the purpose of reducing contact resistance, as recognized by Rahman, and/or providing a barrier for the fill material to protect from diffusion into surrounding materials.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Huang et al. (US Patent No. 10,050,149), hereinafter referred to as Huang.
Regarding claim 8, Xie teaches the structure of claim 1. However, Xie does not explicitly teach the dielectric structure embeds a bottom etch stop layer, wherein the bottom etch stop layer lands on a top surface of the gate, wherein the metal contact and the feedthrough via both penetrate through the bottom etch stop layer.
Huang teaches the dielectric structure embeds a bottom etch stop layer, wherein the bottom etch stop layer lands on a top surface of the gate, wherein the metal contact and the feedthrough via both penetrate through the bottom etch stop layer (Fig. 2, ILD layer 236, gate capping structure 120, gate structure 108, S/D contact structures 228 & 229; Col. 6, lines 36-43).
Xie and Huang are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xie with the etch stop layer of Huang such that the dielectric structure embeds a bottom etch stop layer, wherein the bottom etch stop layer lands on a top surface of the gate, wherein the metal contact and the feedthrough via both penetrate through the bottom etch stop layer. For the purpose of protecting structures in the device during the various manufacturing processes, as recognized by Huang.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Huang as applied to claim 8 above, and further in view of Bouche et al. (Pub. No. US 20220157722 A1), hereinafter referred to as Bouche.
Regarding claim 9, Xie in view of Huang does not explicitly teach a top etch stop layer, wherein the first and second vias penetrate through the top etch stop layer to land on the metal contact and the feedthrough via, respectively.
Bouche teaches a top etch stop layer, wherein a via penetrates through the top etch stop layer to land the feedthrough via (Fig. 7L, etch-stop layer 752, trench contact 330, BPR metal 322; ¶104-118).
Xie, Huang, and Bouche are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xie in view of Huang with the etch stop layer of Bouche such that there is a top etch stop layer, wherein the first and second vias penetrate through the top etch stop layer to land on the metal contact and the feedthrough via, respectively. For the purpose of protecting structures in the device during the various manufacturing processes.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Su and in further view of Chu et al. (Pub. No. US 20250194179 A1), hereinafter referred to as Chu.
Regarding claim 10, Xie teaches the structure of claim 1. However, Xie does not explicitly teach along the first direction, a top width of the feedthrough via is greater than a bottom width of the metal contact.
Su teaches increasing the size of the interface between a via and a source feature in order to lower resistance and having a large via volume to reduce resistance (¶44-45, 49).
Chu teaches shrinking the width of a S/D contact structure in order to have a transistor with a larger channel length without increasing the overall width of the transistor and increased flexibility in ensuring the S/D contact has good current conduction (¶17).
Xie, Su, and Chu are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xie with the larger via teaching of Su and the smaller contact teachings of Chu such that along the first direction, a top width of the feedthrough via is greater than a bottom width of the metal contact. For the purpose of being able to have larger channel lengths as recognized by Chu and to reduce resistance of the device and have good conduction as recognized by both Chu and Su.
Claim(s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Jeon et al. (Pub. No. US 20240186247 A1), hereinafter referred to as Jeon.
Regarding claim 11, Xie teaches a semiconductor structure, comprising: a first circuit area having: an active region extending lengthwise along a first direction, the active region includes a channel region between source/drain (S/D) features and a gate over the channel region, a dielectric structure over and surrounding the active region, a metal contact having a first portion penetrating a first distance into the dielectric structure to land on one of the S/D features, and a first via landing on the metal contact (Fig. 21D & 23A-23C, NFET, PFET, active semiconductor layers 208, high-k metal gate 210, S/D epitaxial layers 214, ILD layer 216, first contact 260, BEOL 263; ¶105-108); and a second circuit area having: a second portion of the metal contact having side surfaces directly contacting the dielectric structure; a feedthrough via adjacent to the second portion of the metal contact and penetrating a second distance into the dielectric structure; and a second via landing on the feedthrough via, wherein the second distance is greater than the first distance (Fig. 21D & 23A-23C, ILD layer, power rail 262, BEOL layer 263; ¶105-108). However, Xie does not explicitly teach the bottom surface of the metal contact directly contacting the dielectric structure.
Jeon teaches the metal contact having a bottom surface directly contacting the dielectric structure (Figs. 2, 7, 15-20, first source drain contact CA1, second source drain contact CA2, interlayer insulating film 110; ¶79, 133-135).
Xie and Jeon are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xie to incorporate the teaching of Jeon such that the metal contact has a bottom surface directly contacting the dielectric structure. For the purpose of having the metal contact be larger than the S/D region ensuring full coverage for optimal operation of the device and to isolate the contact from unwanted electrical connections.
Regarding claim 12, Xie further teaches a backside metal below a bottom surface of the dielectric structure, and the feedthrough via lands on a top surface of the backside metal (Fig. 23C, backside power rail VSS 274, power rail 262; ¶105-108).
Regarding claim 13, Xie further teaches the first circuit area further comprising: a second channel region of the active region between second source/drain (S/D) features and a second gate over the second channel region (Fig. 23A, active semiconductor layers 208, high-k metal gate 210, S/D epitaxial layers 214; ¶105-108), and a second metal contact having a first portion penetrating the first distance into the dielectric structure to land on one of the second S/D features, wherein the second circuit area further includes a second portion of the second metal contact, and the feedthrough via is laterally disposed between the first and second metal contacts along the first direction (Fig. 23C, first contact 260, ILD layer 216, S/D epitaxial layer 214, power rail 262; ¶105-108). However, Xie does not explicitly teach a second portion of the second metal contact landing on another horizontal surface of the dielectric structure.
Jeon teaches a second portion of the second metal contact landing on another horizontal surface of the dielectric structure (Figs. 2, 7, 15-20, first source drain contact CA1, second source drain contact CA2, interlayer insulating film 110; ¶79, 133-135).
Xie and Jeon are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xie to incorporate the teaching of Jeon such that a second portion of the second metal contact landing on another horizontal surface of the dielectric structure. For the purpose of having the metal contact be larger than the S/D region ensuring full coverage for optimal operation of the device and to isolate the contact from unwanted electrical connections.
Regarding claim 14, Xie does not explicitly teach the feedthrough via having a top width along the first direction, a bottom width along the first direction, and the bottom width being greater than the top width.
Jeon teaches the feedthrough via having a top width along the first direction, a bottom width along the first direction, and the bottom width being greater than the top width (Fig. 9, first through-via TV1, second through-via TV2; ¶122).
Xie and Jeon are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xie to incorporate the teaching of Jeon such that the feedthrough via has a top width along the first direction, a bottom width along the first direction, and the bottom width is greater than the top width. For the purpose of being able to perform the etching process for forming the feedthrough via from the backside of the device, as recognized by Jeon.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Jeon as applied to claim 14 above, and further in view of Su and Chu.
Regarding claim 15, Xie in view of Jeon teaches the structure of claim 14. However, Xie in view of Jeon does not explicitly teach the metal contact having a bottom width, and wherein the top width of the feedthrough via is greater than the bottom width of the metal contact.
Su teaches increasing the size of the interface between a via and a source feature in order to lower resistance and having a large via volume to reduce resistance (¶44-45, 49).
Chu teaches shrinking the width of a S/D contact structure in order to have a transistor with a larger channel length without increasing the overall width of the transistor and increased flexibility in ensuring the S/D contact has good current conduction (¶17).
Xie, Jeon, Su, and Chu are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xie in view of Jeon with the larger via teaching of Su and the smaller contact teachings of Chu such that along the first direction, a top width of the feedthrough via is greater than a bottom width of the metal contact. For the purpose of being able to have larger channel lengths as recognized by Chu and to reduce resistance of the device and have good conduction as recognized by both Chu and Su
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Jeon as applied to claim 11 above, and further in view of Huang.
Regarding claim 16, Xie does not explicitly teach the dielectric structure embeds a bottom etch stop layer, wherein the bottom etch stop layer lands on a top surface of the gate, wherein the metal contact and the feedthrough via both penetrate through the bottom etch stop layer.
Huang teaches the dielectric structure embeds a bottom etch stop layer, wherein the bottom etch stop layer lands on a top surface of the gate, wherein the metal contact and the feedthrough via both penetrate through the bottom etch stop layer (Fig. 2, ILD layer 236, gate capping structure 120, gate structure 108, S/D contact structures 228 & 229; Col. 6, lines 36-43).
Xie and Huang are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xie with the etch stop layer of Huang such that the dielectric structure embeds a bottom etch stop layer, wherein the bottom etch stop layer lands on a top surface of the gate, wherein the metal contact and the feedthrough via both penetrate through the bottom etch stop layer. For the purpose of protecting structures in the device during the various manufacturing processes, as recognized by Huang.
Claim(s) 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Rahman.
Regarding claim 21, Xie teaches a semiconductor structure, comprising: active regions extending lengthwise along a first direction, each of the active regions includes a channel region between source/drain (S/D) features and a gate over the channel region (Figs. 21D & 23A-23C, NFET, PFET, active semiconductor layers 208, high-k metal gate 210, S/D epitaxial layers 214; ¶105-108); a dielectric structure over and surrounding each of the active regions (Fig. 23C, ILD layer 216, p-type S/D epitaxial layers 215, n-type S/D epitaxial layers 214); metal contacts penetrating the dielectric structure to land on the S/D features (Fig. 23C, first contact 260, ILD layer 216, n-type S/D epitaxial layers 214, p-type S/D epitaxial layers 215; ¶105-108); a feedthrough via completely penetrating through the dielectric structure and disposed between adjacent metal contacts along the first direction (Fig. 23C, power rail 262, ILD layer 216, first contact 260; ¶105-108); a first via landing on one of the metal contacts (Fig. 23A-23C, BEOL layer 263; ¶105-108). However, Xie does not explicitly teach a second via landing on the feedthrough via and is isolated from the metal contacts.
Rahman teaches a second via landing on the feedthrough via and is isolated from the metal contacts (Fig. 4A, deep trench via 226, interconnect layers 406, interconnect structure 428; ¶58-64).
Xie and Rahman are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the structure of Xie with the vias of Rahman such that the second via lands on the feedthrough via and is isolated from the metal contacts. For the purpose of having desired electrical connections for optimal operation of the device.
Regarding claim 22, Xie further teaches the feedthrough via being disposed between adjacent active regions along a second direction different from the first direction (Fig. 21D, power rail 262, NFET, PFET; ¶105-108).
Regarding claim 23, Xie further teaches each of the adjacent active regions have a uniform width along the second direction that extends along the first direction (Figs. 17A & 17B3, NFET, PFET; ¶98-102).
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/E.A.T./ Examiner, Art Unit 2897
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