DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group II, claims 1-14, in the reply filed on 05/19/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ahn et al. (US 2008/0068879 A1), hereafter “Ahn”.
As to claim 1, Ahn teaches a memory structure, comprising:
a bottom via (WL1, Fig. 4, ⁋ [0051]);
a memory cell (Fig 2, 100, ⁋ [0051]) disposed on the bottom via, and comprising:
a bottom electrode (Fig. 4, 59, ⁋ [0045]);
a top electrode (73, ⁋ [0056]); and
a first storage element layer (Fig. 4, 65b, ⁋ [0056], “high temperature phase change material”) and a second storage element layer (71b, “low temperature phase change material”) sandwiched between the bottom electrode and the top electrode, wherein the first storage element layer (65b) is in contact (in contact via BEC/63, ⁋ [0055]) with the bottom electrode (59), and wherein a crystallization temperature of the first storage element layer is higher than a crystallization temperature of the second storage element layer (⁋ [0056], “the low temperature phase change material may have a crystallization temperature that is lower than a crystallization temperature of the high temperature phase change material”); and
a top via (BL1, Fig. 4, ⁋ [0051]) disposed on the memory cell and electrically connected to the top electrode.
Claims 8-10, 12, 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Trinh et al. (US 2021/0066587 A1), hereafter “Trinh ‘587”.
As to claim 8, Trinh ‘587 teaches a semiconductor device, comprising:
a device region (Fig. 1, 100, ⁋ [0018]) disposed on a substrate (102, ⁋ [0019]);
a first interconnect structure (Fig. 5, 116, ⁋ [0019]) connected to the device region, and located on the substrate;
a memory structure (122+120+512+136, ⁋⁋ [0018], [0019], [0039], [0020]) disposed on the first interconnect structure, wherein the memory structure comprises:
a bottom via (120) connected to the first interconnect structure;
a memory cell (122) disposed on the bottom via and comprising a bottom electrode (124, ⁋ [0020]), a first storage element layer (130+132, ⁋ [0018]), a second storage element layer (128), a capping layer ( 508, ⁋ [0037]) and a top electrode (Fig. 1, 134, ⁋ [0020]) stacked up in sequence over the bottom via, wherein the first storage element layer (130+132) comprises a combination of a first material having a bandgap of 5eV or less (⁋ [0025], “the second data storage layer 130 may comprise a material with a bandgap within a range of about 3.5 to 5.5 eV”), and at least one second material having a bandgap of 6eV or more(⁋ [0025], “third data storage layer 132 may comprise aluminum oxide (e.g., Al.sub.2O.sub.3), thereby having a bandgap of about 8.5 eV”), and the second storage element layer (128) comprises a material different than that of the first storage element layer (⁋ [0024], several materials are mentioned as possible material for 128 but not 130+132); and
a top via (136) disposed on the memory cell and electrically connected to the top electrode; and
a second interconnect structure (138, ⁋ [0020]) disposed on the memory structure and electrically connected to the top via.
As to claim 9, Trinh ‘587 teaches the semiconductor device according to claim 8, and further teaches wherein the first material of the first storage element layer is tantalum oxide (⁋ [0024], 130 can be tantalum aluminum oxide) the at least one second material of the first storage element layer is aluminum oxide (⁋ [0024], 132 can be aluminum oxide), silicon oxide, or a combination of aluminum oxide and silicon oxide, but fails to teach.
As to claim 10, Trinh ‘587 teaches the semiconductor device according to claim 8, wherein a sum of a thickness of the first storage element layer and a thickness of the second storage element layer is in a range of 10 angstroms to 100 angstroms (⁋ [0024], layer 128 to 5 to 20 Angstroms, layer 130 5 to 20 Angstroms and layer 132 10 to 40).
As to claim 12, Trinh ‘587 teaches the semiconductor device according to claim 8, and further teaches wherein a crystallization temperature of the first storage element layer is higher than a crystallization temperature of the second storage element layer. Trinh ‘587 teaches some of the same materials for the first storage element layers (⁋ [0024], aluminum oxide, tantalum aluminum oxide) and second storage element layer (⁋ [0024], hafnium tantalum oxide) as the instant application and therefore Trinh ‘587 would teach the limitation.
As to claim 14, Trinh ‘587 teaches the semiconductor device according to claim 8, wherein the memory structure further comprises a spacer structure (510, ⁋ [0037]) disposed on the first storage element layer and laterally surrounding the second storage element layer, the capping layer and the top electrode (⁋ [0037], “laterally surrounds sidewalls of the memory cell 122”).
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn, and further in view of Cheng (US 2021/0210682 A1), hereafter “Cheng ‘682”.
As to claim 2, Ahn teaches the structure according to claim 1, and further teaches the first storage element layer comprising a phase change material GeSb but fails to teach wherein the first storage element layer comprises a combination of tantalum oxide and aluminum oxide, or a combination of tantalum oxide and silicon oxide.
Cheng ‘682 teaches a similar device wherein a phase change material layer (160) comprising GST that can be doped with Aluminum Oxide, Silicon Oxide, and/or tantalum oxide (⁋ [0148]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of doping the phase change material with the aforementioned material taught by Cheng ‘682 into the device of Ahn since it would’ve been a well-known method for a phase change layer at the time of the invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Anh, Cheng’ 682 and further in view of Trinh et al. (US 2022/0302381 A1), hereafter “Trinh ‘381”.
As to claim 3, Ahn in view of Cheng ‘682 teaches the structure according to claim 2, Cheng ‘682 further teaches the first storage element layer comprising of tantalum oxide and aluminum oxide, but fails to teach wherein when the first storage element layer comprises the combination of tantalum oxide and aluminum oxide, an atomic profile of aluminum is higher at a bottom surface of the first storage element layer than at a top surface of the first storage element layer, and when the first storage element layer comprises the combination of tantalum oxide and silicon oxide, an atomic profile of silicon is higher at the bottom surface of the first storage element layer than at the top surface of the first storage element layer.
Trinh ‘381 teaches a device in the same field of endeavor wherein a data storage structure (414, Fig. 4, ⁋ [0035]) comprised of an aluminum oxide (⁋ [0036]) wherein the concentration of aluminum decreases the further away from the lower electrode (408) (Fig. 2, ⁋⁋ [0023]-[0024], [0037]-[0039]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the concentration of aluminum dispersion as taught by Trinh ‘381 into the device of Ahn in view of Cheng ‘682 because the higher oxygen vacancy density would provide for good data retention (⁋⁋ [0020]-[0022]). One skilled in the art would be inclined to combine the references in order to prevent loss of information within a memory device.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Anh, and further in view of Park et al. (US 2020/0075854 A1), hereafter “Park”.
As to claim 4, Ahn teaches the structure according to claim 1, and further teaches the second storage element layer (71b) comprising a phase change material GeTe but fails to teach wherein the second storage element layer is a material selected from the group consisting of zirconium tantalum oxide (ZrTaO), hafnium tantalum oxide (HffaO), hafnium aluminum oxide (HfAIO), hafnium oxide (HfO2), and zirconium oxide (ZrO2).
Park teaches a similar device wherein a phase change pattern (140, Fig. 2A, ⁋ [0017]) may comprise zirconium oxide (⁋ [0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of doping the phase change material with the aforementioned material taught by Cheng into the device of Ahn since Park teaches that zirconium oxide may be substituted for GeTe (⁋ [0026]).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Anh, and further in view of Chen et al. (US 2023/0284540 A1), hereafter “Chen”.
As to claim 5, Ahn teaches the memory structure according to claim 1, but fails to teach wherein the memory cell further comprises: a capping layer located in between the second storage element layer and the top electrode; and a barrier layer located in between the bottom electrode and the bottom via.
Chen teaches a device in a similar field of endeavor in which a capping layer (115, Fig. 21, ⁋ [0080]) is formed between a switching layer i.e. storage element (113, ⁋ [0086]) and top electrode (117, ⁋ [0080]) and a barrier layer (109, ⁋ [0086]) formed between a bottom electrode (111, ⁋ [0086]) and bottom via (103, ⁋ [0057]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the capping layer as taught by Chen into the device of Ahn to provide an oxygen storage function that facilitates phase changes in switching layer (⁋ [0129]).
Additionally, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the barrier layer as taught by Chen into the device of Ahn due to the barrier layer functioning as a diffusion barrier that prevents or substantially inhibits diffusion of the material(s) of nearby metal features into the bottom electrode (⁋ [0067]).
As to claim 6, Ahn in view of Chen teach the memory structure according to claim 5, Chen teaches further comprising a spacer structure (129, Fig. 21, ⁋ [0093]) laterally surrounding the second storage element layer (113), the capping layer (115) and the top electrode (117).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of a spacer surrounding the memory cell as taught by Chen into the modified device of Ahn and Chen as one skilled in the art would understand spacers are used to protect the structures such as the memory cell from damage or interference.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Anh, and further in view of Trinh ‘381.
As to claim 7, Ahn teaches the memory structure according to claim 1, but fails to teach wherein sidewalls of the second storage element layer are retracted from sidewalls of the first storage element layer.
Trinh ‘381 teaches a device in the same field of endeavor wherein a data storage structure (502, Fig. 5, ⁋ [0043]) wherein the plurality of sub-layers 504-506 within the multi-layer data storage structure 502 may have outermost sidewalls that are laterally offset from one another (⁋ [0046]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device of Ahn to include laterally offset sidewalls as taught by Trinh ‘381, as both references are in the same field and address similar multi-layered structures. As explained in MPEP § 2141, the proper analysis is “whether the claimed invention would have been obvious as of the relevant time to one of ordinary skill in the art after consideration of all the facts,” and “factors other than the disclosures of the cited prior art may provide a basis for concluding that it would have been obvious to one of ordinary skill in the art to bridge the gap.”
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Trinh ‘587, and further in view of Trinh ‘381.
As to claim 11, Trinh ‘587 teaches the semiconductor device according to claim 8, but fails to teach wherein the second storage element layer comprises a retracted portion, and sidewalls of the retracted portion are aligned with sidewalls of the capping layer and sidewalls of the top electrode.
Trinh ‘381 teaches a device in the same field of endeavor wherein a data storage structure (502, Fig. 5, ⁋ [0043]) wherein the plurality of sub-layers 504-506 within the multi-layer data storage structure 502 may have outermost sidewalls that are laterally offset from one another (⁋ [0046]) and layer 506 is aligned with sidewalls of the capping layer (508) and upper electrode (420).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device of Ahn to include laterally offset sidewalls as taught by Trinh ‘381, as both references are in the same field and address similar multi-layered structures. As explained in MPEP § 2141, the proper analysis is “whether the claimed invention would have been obvious as of the relevant time to one of ordinary skill in the art after consideration of all the facts,” and “factors other than the disclosures of the cited prior art may provide a basis for concluding that it would have been obvious to one of ordinary skill in the art to bridge the gap.”
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Trinh ‘587, and further in view of Cheng et al. (US 2012/0193595 A1), hereafter “Cheng ‘595”.
As to claim 13, Trinh’ 587 teaches the semiconductor device according to claim 8, but fails to teach wherein the first material and the second material are evenly distributed in the first storage element layer to have a uniform atomic profile of elements from a bottom surface to a top surface of the first storage element layer.
Cheng ‘595 teaches a device in a same field of endeavor (⁋ [0017]) wherein a bi-layer memory material (312, Fig. 9, ⁋ [0049]) contains concentrations that are essentially constant throughout the thickness of the memory layer (⁋ [0050]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the constant concentration distribution as taught by Cheng ‘595 into the device of Trinh ‘587 for better endurance and retention (⁋ [0050]).
Conclusion
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/CARNELL HUNTER III/Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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