Attorney’s Docket Number: NAUP4390USA
Filing Date: 01/10/2024
Claimed Foreign Priority Date: 12/20/2023 (TW112149793)
Applicants: Lin et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed on 07/23/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s elections without traverse of Group Invention I (drawn to a semiconductor structure) and of Species 1 (drawn to Figs. 4-7), in the reply filed on 07/23/2026, is acknowledged. Applicant indicated that claims 1-11 read on the elected Species. The examiner agrees. Accordingly, pending in this application are claims 1-15, with claims 12-15 standing withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group Invention, there being no allowable generic or linking claim.
Drawings
The drawings are objected to because Figs. 7 and 9 erroneously depict bottom electrode plug P1 connected to capacitor dielectric layer 22b, instead of being in contact with bottom electrode 22a, as disclosed in the written description (see, Specification, Par. [0024], L. 20-24).
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the arrangement corresponding to the limitation “an MIM capacitor disposed above the first transistor” (see, claim 6, L. 4) as further limited by the limitation “the deep trench comprises a trench and a first air gap” (see, claim 8, L. 2), must be shown or the features canceled from the claims. The examine contends that once the MIM capacitor is formed by filling the space previously corresponding to TR1 and AG1, as shown in intermediate manufacturing steps (see, Figs. 3-5 or 8), the lower portion of DT1 can no longer be understood as having an “air gap”, at least because the final structure is fully filled with the MIM cap materials (see, Figs. 7 and 9). No new matter should be entered.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “AG1” has been used to designate both an air gap/void in dielectrics 14 and 18a (see, e.g., Figs. 3-5 or 8), and a lower portion of DT1 that is filled with materials 22a-c and 24 (see, e.g., Figs. 7 and 9).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8-10 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Initially, the examiner acknowledges that the use of the term “air gap” is appropriate to describe both “void” features AG1 and AG2 in intermediate manufacturing steps (see, e.g., Figs. 3-5 or 8). However, the use of the term “air gap” in a final structure wherein the MIM capacitor is formed by filling DT1 raises clarity issues, because said “air gap” has been explicitly filled by MIM capacitor materials, and as such does no longer include any “air” (see, Figs. 7 or 9).
As such claim 8 is deemed indefinite, because it is unclear if the limitation recited in claim 8, L. 2 “the deep trench comprises a trench and a first air gap” and further limiting claim 6, requires a “true air gap” at the bottom of DT1 (such as air gap AG2), or merely requires instead a MIM-material-filled gap devoid of air.
In the interest of compact prosecution, and for the purpose of examination, claim 8 will be construed as reciting -- wherein the deep trench comprises a trench and a first
Claims 9 and 10 depend from claim 8, thus inherit the deficiencies identified supra.
Claim 9 recites “wherein a bottom of the trench and an opening of the first air gap form a second stepped profile”. See comments stated above with regards to claim 8, which are considered repeated here. Similarly, and for the purpose of examination, claim 9 will be construed as reciting -- wherein a bottom of the trench and an opening of the first
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US2016/0020270).
Regarding Claim 1, Kim (see, e.g., Fig. 1 and Par. [0028]-[0035]) shows all aspects of the instant invention, including a semiconductor structure with a metal-insulator-metal (MIM) capacitor (e.g., DC-to-DC converter having MIM capacitors), comprising:
- a first transistor, wherein the first transistor comprises a source and a drain (e.g., transistor comprising source region 104 and a drain region 105)
- an interlayer dielectric layer (e.g., inter-layer insulation layer 107) covering the first transistor
- a source plug (e.g., contact plug 108A) penetrating the interlayer dielectric layer and contacting the source
- a drain plug (e.g., contact plug 108B) penetrating the interlayer dielectric layer and contacting the drain
- a metal interlayer dielectric layer (e.g., inter-layer insulation layer 109 including metal lines Mx) covering the interlayer dielectric layer
- an MIM capacitor (e.g., capacitor 110 having metal bottom/top plates 110A/110C and high-k dielectric layer 110B therebetween) disposed in the interlayer dielectric layer and the metal interlayer dielectric layer.
Regarding Claim 3, Kim (see, e.g., Fig. 1) shows a deep trench disposed in the metal interlayer dielectric layer and the interlayer dielectric layer (see, e.g., Fig. 3e and Par. [0051]: openings 20), wherein the MIM capacitor comprises a bottom electrode, a capacitor dielectric layer and a top electrode covering the deep trench in sequence (see, e.g., Par. [0035]: bottom plates 110A, dielectric layer 110B, and top plate 110C).
Claims 6-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US6630380).
Regarding Claim 6, Cheng (see, e.g., Fig. 2) shows all aspects of the instant invention, including a semiconductor structure with a metal-insulator-metal (MIM) capacitor, comprising:
- a first transistor (e.g., FET transistor comprising 14,16,17-19)
- an MIM capacitor (e.g., MIM capacitor comprising 28,30,32) disposed above the first transistor, wherein the MIM capacitor comprises a first stepped profile.
Regarding Claim 7, Cheng (see, e.g., Fig. 2) shows:
- an interlayer dielectric layer (e.g., insulating layer 20) covering the first transistor
- a metal interlayer dielectric layer (e.g., insulating layer 24 comprising metal conductive layer 26) covering the interlayer dielectric layer
- a deep trench (see, e.g., Fig. 1: opening 1) disposed in the metal interlayer dielectric layer and the interlayer dielectric layer.
Claims 1, 3-4, and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Durcan et al. (US6159818).
Regarding Claim 1, Durcan (see, e.g., Figs. 11-12) shows all aspects of the instant invention, including a semiconductor structure with a metal-insulator-metal (MIM) capacitor, comprising:
- a first transistor, wherein the first transistor comprises a source and a drain (e.g., one of transistors 16 comprising source region 14A and a drain region 14B)
- an interlayer dielectric layer (e.g., dielectric layer 18) covering the first transistor
- a source plug (e.g., one of conductive studs 15) penetrating the interlayer dielectric layer and contacting the source
- a drain plug (e.g., another one of conductive studs 15) penetrating the interlayer dielectric layer and contacting the drain
- a metal interlayer dielectric layer (e.g., dielectric layer 19 including conductive layer 36) covering the interlayer dielectric layer
- an MIM capacitor (e.g., capacitor 8C having metal (ruthenium) bottom/top electrodes 20/24C and dielectric layer 23C therebetween) disposed in the interlayer dielectric layer and the metal interlayer dielectric layer.
Regarding Claim 3, Durcan (see, e.g., Figs. 11-12) shows a deep trench disposed in the metal interlayer dielectric layer (e.g., 19) and the interlayer dielectric layer (e.g., 18), wherein the MIM capacitor comprises a bottom electrode (e.g., bottom electrode 20), a capacitor dielectric layer (e.g., dielectric layer 23C) and a top electrode (e.g., top electrode 20) covering the deep trench in sequence.
Regarding Claim 4, Durcan (see, e.g., Figs. 11-12) shows that an end of the deep trench is disposed in the interlayer dielectric layer (e.g., 18) and the end is disposed directly above a first gate of the first transistor (e.g., 16).
Regarding Claim 6, Durcan (see, e.g., Figs. 11-12) shows all aspects of the instant invention, including a semiconductor structure with a metal-insulator-metal (MIM) capacitor, comprising:
- a first transistor (e.g., one of transistors 16)
- an MIM capacitor (e.g., MIM capacitor 8C having metal (ruthenium) bottom/top electrodes 20/24C and dielectric layer 23C therebetween) disposed above the first transistor, wherein the MIM capacitor comprises a first stepped profile.
Regarding Claim 7, Durcan (see, e.g., Figs. 11-12) shows:
- an interlayer dielectric layer (e.g., dielectric layer 18) covering the first transistor
- a metal interlayer dielectric layer (e.g., dielectric layer 19 including conductive layer 36) covering the interlayer dielectric layer
- a deep trench disposed in the metal interlayer dielectric layer (e.g., 19) and the interlayer dielectric layer (e.g., 18).
Regarding Claim 8, Durcan (see, e.g., Figs. 11-12) shows that the deep trench comprises a trench (e.g., trench portion in 19 and 18) and a first gap (e.g., trench portion between 16s), the trench is connected to the first gap, the trench is disposed on the first gap, and a width of the trench is greater than a width of the first gap.
Regarding Claim 9, Durcan (see, e.g., Figs. 11-12) shows that a bottom of the trench and an opening of the first gap form a second stepped profile.
Regarding Claim 10, Durcan (see, e.g., Figs. 11-12) shows that the MIM capacitor contacts a sidewall of the deep trench.
Claims 1-3 and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kitamura et al. (US2002/0113237).
Regarding Claim 1, Kitamura (see, e.g., Fig. 2) shows all aspects of the instant invention, including a semiconductor structure with a metal-insulator-metal (MIM) capacitor, comprising:
- a first transistor, wherein the first transistor comprises a source and a drain (e.g., one of MOS transistors comprising source region 13 and a drain region 14)
- an interlayer dielectric layer (e.g., inter-level dielectric 16) covering the first transistor
- a source plug (e.g., plug 17) penetrating the interlayer dielectric layer and contacting the source
- a drain plug (e.g., plug 18) penetrating the interlayer dielectric layer and contacting the drain
- a metal interlayer dielectric layer (e.g., inter-level dielectric 22 including metal contact 30) covering the interlayer dielectric layer
- an MIM capacitor (e.g., capacitor having metallic bottom/top electrodes 6/8 and dielectric layer 7 therebetween) disposed in the interlayer dielectric layer and the metal interlayer dielectric layer.
Regarding Claim 2, Kitamura (see, e.g., Fig. 2) shows the MIM capacitor is sandwiched between the source plug and the drain plug (e.g., lower portion of 6 is laterally arranged between 17 and 18).
Regarding Claim 3, Kitamura (see, e.g., Fig. 2) shows a deep trench disposed in the metal interlayer dielectric layer (e.g., 22) and the interlayer dielectric layer (e.g., 16), wherein the MIM capacitor comprises a bottom electrode (e.g., bottom electrode 6), a capacitor dielectric layer (e.g., dielectric layer 7) and a top electrode (e.g., top electrode 8) covering the deep trench in sequence.
Regarding Claim 6, Kitamura (see, e.g., Fig. 2) shows all aspects of the instant invention, including a semiconductor structure with a metal-insulator-metal (MIM) capacitor, comprising:
- a first transistor (e.g., one of MOS transistors)
- an MIM capacitor (e.g., capacitor having metallic bottom/top electrodes 6/8 and dielectric layer 7 therebetween) disposed above the first transistor, wherein the MIM capacitor comprises a first stepped profile.
Regarding Claim 7, Kitamura (see, e.g., Fig. 2) shows:
- an interlayer dielectric layer (e.g., dielectric layer 16) covering the first transistor
- a metal interlayer dielectric layer (e.g., dielectric layer 22 including conductive layer 36) covering the interlayer dielectric layer
- a deep trench disposed in the metal interlayer dielectric layer (e.g., 22) and the interlayer dielectric layer (e.g., 16).
Regarding Claim 8, Kitamura (see, e.g., Fig. 2) shows that the deep trench comprises a trench (e.g., trench portion in 22) and a first gap (e.g., trench portion in 16), the trench is connected to the first gap, the trench is disposed on the first gap, and a width of the trench is greater than a width of the first gap.
Regarding Claim 9, Kitamura (see, e.g., Fig. 2) shows that a bottom of the trench and an opening of the first gap form a second stepped profile.
Regarding Claim 10, Kitamura (see, e.g., Fig. 2) shows that the MIM capacitor contacts a sidewall of the deep trench.
Allowable Subject Matter
Claims 5 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose semiconductor structures including a MIM capacitor and having features similar to the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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