Prosecution Insights
Last updated: October 01, 2026
Application No. 18/408,820

Die Stacking with Integrated Thermal Treatment

Non-Final OA §102§103
Filed
Jan 10, 2024
Priority
Nov 17, 2023 — provisional 63/600,588
Examiner
ASSOUMAN, HERVE-LOUIS Y
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Applied Materials Inc.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
627 granted / 686 resolved
+23.4% vs TC avg
Minimal +4% lift
Without
With
+4.1%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
31 currently pending
Career history
713
Total Applications
across all art units

Statute-Specific Performance

§101
3.3%
-36.7% vs TC avg
§103
59.1%
+19.1% vs TC avg
§102
18.7%
-21.3% vs TC avg
§112
8.3%
-31.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 686 resolved cases

Office Action

§102 §103
Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Election/Restrictions Applicant's election with traverse of claims 1-17 in the reply filed on 06/22/2026 is acknowledged. The traversal is on the ground(s) that the Examiner has not demonstrated that there is a serious search burden. This is not found persuasive because Invention II drawn to claims 18-20 are not even examined in the Technology Center of 2800, let alone in class 438 and 257, which correspond to the classes examined by Examiner. Moreover, it would require different search strategies and group/subgroup areas not familiar to Examiner adding more complexity to search burden. Claims 17-20 will be examined by a different examiner in a different Technology Center. Applicant has not shown why Examiner should examine claims not examined in his Technology Center or examination area. Therefore, the restriction requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3, 6 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uzoh (US 2018/0182654 A1), hereinafter Uzoh654. Regarding independent claim 1: Uzoh654 teaches (e.g., Fig. 1) a substrate processing method, comprising: sequentially stacking a plurality of dies (Fig. 1; [0035]-[0036]; step 8 to 21; the looping of the steps results in sequentially stacking a plurality of dies) on a substrate into a stacked assembly (Fig. 1; step 8 to 21; substrate; the looping meets the following requirement “approximately 13+7(n−1); n>0 steps to complete (where n=the desired quantity of dies in the stack)”); thermally treating the plurality of dies ([0035]-[0036]); and stacking at least one additional die atop the thermally treated plurality of dies ([0035]-[0036]; the looping meets the following requirement “approximately 13+7(n−1); n>0 steps to complete (where n=the desired quantity of dies in the stack)”). Regarding claim 3: Uzoh654 teaches the claim limitation of the method of claim 1, on which this claim depends, wherein thermally treating is performed after stacking a certain number of dies of the plurality of dies on the substrate ([0035]-[0036]: step 20 is repeated according to 13+7(n−1); n>0 steps to complete; this meets the claim limitation requirement). Regarding claim 6: Uzoh654 teaches the claim limitation of the method of claim 1, on which this claim depends. wherein thermally treating includes contacting at least one of the plurality of dies using a thermally conductive structure ([0033], [0035]). Regarding claim 9: Uzoh654 teaches the claim limitation of the method of claim 1, on which this claim depends, further comprising cleaning and activating a backside of each die (Fig. 1, step 4 to 21). Regarding claim 10: Uzoh654 teaches the claim limitation of the method of claim 9, on which this claim depends, wherein activating includes plasma treatment ([0033]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh (US 2018/0182654 A1), hereinafter Uzoh654 in view of Kang et al. (US 20230087198 A1). Regarding claim 2: Uzoh654 teaches the claim limitation of the method of claim 1, on which this claim depends, further comprising annealing the stacked assembly and the at least one additional die after stacking the at least one additional die ([0035]-[0036]: step 20 is repeated according to 13+7(n−1); n>0 steps to complete; this meets the claim limitation requirement). Uzoh654 does not expressly teach that the method of thermally treating is performed at at least one of a lower temperature or a shorter duration than the annealing. Kang teaches (e.g., Fig. 2) a method comprising thermally treating being performed at at least one of a lower temperature or a shorter duration than an annealing ([0061]: the pre-annealing corresponds to the method of thermally treating a chip; the method is performed at a lower temperature and a shorter duration than an annealing process). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Uzoh654, the method of thermally treating being performed at at least one of a lower temperature or a shorter duration than the annealing, as taught by Kang, for the benefits of activating the bonding surface before the annealing and thus improving the bonding strength of the chip stacks. Regarding claim 15: Uzoh654 teaches the claim limitation of the method of claim 1, on which this claim depends. wherein thermally treating is performed at a substrate temperature of 100° C. to 400° C. Kang teaches (e.g., Fig. 2) a method comprising thermally is performed at a substrate temperature of 100° C. to 400° C ([0061]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Uzoh654, the method of thermally treating being performed at at least one of a lower temperature or a shorter duration than the annealing, as taught by Kang, for the benefits of activating the bonding surface before the annealing and thus improving the bonding strength of the chip stacks. Regarding claim 16: Uzoh654 teaches the claim limitation of the method of claim 1, on which this claim depends. Uzoh654 does not expressly teach that thermally treating is performed for 0.5 minutes to 1 hour. Kang teaches a method comprising thermally treating a surface is performed for 0.5 minutes to 1 hour ([0061]: about 5 minutes to about 10 minutes). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Uzoh654, the method of thermally treating being performed for 0.5 minutes to 1 hour, as taught by Kang, for the benefits of gradually activating the bonding surface and thus improve the reliability and quality of the bonding process Regarding claim 17: Uzoh654 teaches the claim limitation of the method of claim 1, on which this claim depends. Uzoh654 does not expressly teach that thermally treating includes ramping temperature up to 100° C. per second. Kang teaches (e.g., Fig. 2) a method comprising thermally treating a bonding surface includes ramping temperature up to 100° C. per second ([0061]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Uzoh654, the method of thermally treating a bonding surface including ramping temperature up to 100° C. per second, as taught by Kang, for the benefits of gradually activating the bonding surface and thus improve the reliability and quality of the bonding process. Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh (US 2018/0182654 A1), hereinafter Uzoh654. Regarding claim 4: Uzoh654 teaches the claim limitation of the method of claim 3, on which this claim depends. Although Uzoh654 does not expressly teach that the certain number is less than or equal to half of the plurality of dies, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to select a number of treatment, such that the number is equal to half of the plurality of dies, for the benefits of reducing the time of bonding process and thus increasing manufacturing throughput. Regarding claim 5: Uzoh654 teaches the claim limitation of the method of claim 1, on which this claim depends. Although Uzoh654 does not expressly teach that thermally treating and stacking are performed in separate processing chambers of an integrated bonder system. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to choose to perform the thermal treatment in separate processing chambers of an integrated bonder system, specially for reducing cross contamination of changing the bonding environment based on the chip device type and bonding conditions, including temperature or pressure limitations, so as to meet the desired process characteristics. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Uzoh (US 2018/0182654 A1), hereinafter Uzoh654 in view of Yu (US 2022/0334310 A1). Regarding claim 7: Uzoh654 teaches the claim limitation of the method of claim 1, on which this claim depends. Uzoh654 does not expressly teach that thermally treating includes applying a pressure on at least one die of the plurality of dies. Yu teaches (Figs. 1A-1B) a method comprising thermally treating includes applying a pressure on at least one die of the plurality of dies ([0036]-[0037]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Uzoh654, the method of thermally treating including applying a pressure on at least one die of the plurality of dies, as taught by Yu, for the benefits of increasing the bonding strength of the chips, and thus improve device reliability. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Uzoh (US 2018/0182654 A1), hereinafter Uzoh654 in view of Yu (US 2022/0334310 A1) as applied above and further in view of Lo (US 2023/0061189 A1). Regarding claim 8: Uzoh654 and Yu teach the claim limitation of the method of claim 7, on which this claim depends Uzoh as modified by Yu does not expressly teach that the pressure is about 10 to about 100 MPa. Lo teaches (e.g., Figs. 1-14) a method comprising applying a pressure of about 10 to about 100 MPa ([0053]: about 100 MPa and about 150 MPa; this is an overlapping range pressure with about 10 to about 100). Applicant is reminded that a prima facie case of obviousness typically exists when the ranges of a claimed composition overlap the ranges disclosed in the prior art or when the ranges of a claimed composition do not overlap but are close enough such that one skilled in the art would have expected them to have the same properties. In re Peterson, 65 USPQ2d 1379 (CA FC 2003). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Uzoh654 as modified by Yu, the pressure being about 10 to about 100 MPa, as taught by Lo, for the benefits of further improving the bonding quality. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Uzoh (US 2018/0182654 A1), hereinafter Uzoh654 in view of (Liu et al. US 10,790,260 B2). Regarding claim 11: Uzoh654 teaches the claim limitation of the method of claim 9, on which this claim depends. Uzoh654 does not expressly teach that activating includes wet chemistry activation. Liu teaches (e.g., Fig. 5) a method comprising activating including wet chemistry activation (Col. 10, Lines 10-23). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Uzoh654, the method of activating including wet chemistry activation, as taught by Liu, for the benefits of reducing aggressive chemicals during the bonding process and also reduce the process cost, since water is more abundant than most chemicals. Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh (US 2018/0182654 A1), hereinafter Uzoh654 in view of Krasulick et al. (US 2012/0057816 A1). Regarding claim 12: Uzoh654 teaches the claim limitation of the method of claim 1, on which this claim depends. Uzoh654 does not expressly teach that thermally treating is performed in a vacuum. Krasulick teaches (e.g., Figs. 3-7) a method comprising thermally treating a surface is performed in a vacuum ([0046]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Uzoh654, the method comprising thermally treating being performed in a vacuum, for the benefit of reducing surface impurities, and thus, improving the bonding process reliability. Regarding claim 14: Uzoh654 teaches the claim limitation of the method of claim 1, on which this claim depends. Uzoh654 does not expressly teach wherein thermally treating is performed in an inert gas environment or a reducing environment. Krasulick teaches (e.g., Figs. 3-7) a method comprising thermally treating is performed in an inert gas environment or a reducing environment. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Uzoh654, the method comprising thermally treating being performed in a vacuum, for the benefit of reducing surface impurities, and thus, improving the bonding process reliability. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Uzoh (US 2018/0182654 A1), hereinafter Uzoh654 in view of Yonehara et al. (US 2003/0159644 A1). Regarding claim 13: Uzoh654 teaches the claim limitation of the method of claim 1, on which this claim depends. Uzoh654 does not expressly teach thermally treating is performed at a pressure of 3 mTorr to 760 Torr. Yonehara teaches a method comprising thermally treating a surface being performed at a pressure of 3 mTorr to 760 Torr ([0318]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to include in the method of Uzoh654, the method comprising thermally treating a surface being performed at a pressure of 3 mTorr to 760 Torr, as taught by Yonehara, for the benefits of reducing unwanted particle deposition of the bonding surface and thus improving the bonding reliability. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee, hereinafter Lee948, (US 2020/0126948 A1) Figs. 1-4 teaches a substrate processing method, comprising: sequentially stacking at least one die on a substrate into a stacked assembly (Step S40; [0062]-[0063]); thermally treating the plurality of dies (Step S50; [0063]-[0064]); and stacking at least one additional die atop the thermally treated plurality of dies ([0063]-[0064]). Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812
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Prosecution Timeline

Jan 10, 2024
Application Filed
Feb 16, 2024
Response after Non-Final Action
Nov 13, 2024
Response after Non-Final Action
Sep 04, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
96%
With Interview (+4.1%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 686 resolved cases by this examiner. Grant probability derived from career allowance rate.

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