DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I and Species A in the reply filed on 6/26/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 7-8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/26/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-6, 9, 11, 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeong et al (US 2022/0262911; hereinafter Yeong).
Regarding claim 1, Figs 1, 6, 19A-19C, 20A-20C of Yeong discloses a semiconductor device comprising:
a first plurality of nanostructures (56A in 50N; Figs 6/19A; ¶ [0058]) and a second plurality of nanostructures (56B in 50P; Figs 6/19A; ¶ [0058]) over a substrate (50; Fig 19A; ¶ [0014]);
a first gate stack (104/102; Fig 19A; ¶ [0060]) extending between the nanostructures of the first plurality of nanostructures (56A; Fig 19A; ¶ [0058]) and a second gate stack (104/102; Fig 19A; ¶ [0060]) extending between the nanostructures of the second plurality of nanostructures (56B; Fig 19A; ¶ [0058]);
a first source/drain region (88 in 50N/82; Figs 6/19A; ¶ [0064]) in contact with a first nanostructure (56A; Fig 19A; ¶ [0058]) of the first plurality of nanostructures;
a second source/drain region (88 in 50P/82; Figs 6/19A; ¶ [0064]) in contact with a first nanostructure of the second plurality of nanostructures (56B; Fig 19A; ¶ [0058]), wherein the second source/drain region is separated from the first source/drain region (Fig 6);
a silicide layer (108; Fig 19A; ¶ [0064]) between the first source/drain region (88 in 50N; Figs 6/19A; ¶ [0064]) and the second source/drain region (88 in 50P; Figs 6/19A; ¶ [0064]); and
isolation layer (60; Fig 19A; ¶ [0014]) between the silicide layer (108; Fig 19A; ¶ [0064]) and the substrate (50; Fig 19A; ¶ [0014]).
Regarding claim 5, Figs 1, 6, 19A-19C, 20A-20C of Yeong discloses the first source/drain region (88 in 50N/82; Figs 6/19A; ¶ [0064]) is in contact with a second nanostructure of the first plurality of nanostructures (56B in 50P; Figs 6/19A; ¶ [0058]), wherein the first source/drain region extends continuously from the first nanostructure to the second nanostructure and wherein the first nanostructure and the second nanostructure are separated by the first gate stack. (Fig 6)
Regarding claim 6, Figs 1, 6, 19A-19C, 20A-20C of Yeong discloses the silicide layer (108; Fig 19A; ¶ [0064]) comprises a first portion in contact with the first source/drain region (88 in 50N/82; Figs 6/19A; ¶ [0064]) and a second portion in contact the second source/drain region and wherein a metal layer is between the first portion and the second portion. (Fig 6)
Regarding claim 9, Figs 1, 6, 19A-19C, 20A-20C of Yeong discloses a semiconductor device comprising:
a first plurality of nanostructures (56A in 50N; Figs 6/19A; ¶ [0058]) and a second plurality of nanostructures (56B in 50P; Figs 6/19A; ¶ [0058]) over a substrate (50; Fig 19A; ¶ [0014]);
a first gate stack (104/102; Fig 19A; ¶ [0060]) extending between the nanostructures of the first plurality of nanostructures (56A; Fig 19A; ¶ [0058]) and a second gate stack (104/102; Fig 19A; ¶ [0060]) extending between the nanostructures of the second plurality of nanostructures (56B; Fig 19A; ¶ [0058]);
a first source/drain region (88 in 50N/82; Figs 6/19A; ¶ [0064]) in contact with a first nanostructure (56A; Fig 19A; ¶ [0058]) of the first plurality of nanostructures;
a second source/drain region (88 in 50P/82; Figs 6/19A; ¶ [0064]) in contact with a first nanostructure of the second plurality of nanostructures (56B; Fig 19A; ¶ [0058]), wherein the second source/drain region is separated from the first source/drain region (Fig 6);
a silicide layer (108; Fig 19A; ¶ [0064]) between the first source/drain region (88 in 50N; Figs 6/19A; ¶ [0064]) and the second source/drain region (88 in 50P; Figs 6/19A; ¶ [0064]); and
a material layer (60; Fig 19A; ¶ [0014]) between the silicide layer (108; Fig 19A; ¶ [0064]) and the substrate (50; Fig 19A; ¶ [0014]).
Regarding claim 11, Figs 1, 6, 19A-19C, 20A-20C of Yeong discloses a third source/drain region (88 in 50N/82; Figs 6/19A; ¶ [0064]) along a sidewall of a second nanostructure (56B; Fig 19A; ¶ [0058]) of the first plurality of nanostructures, wherein the silicide layer (108; Fig 19A; ¶ [0064]) is between the first source/drain region and the third source/drain region.
Regarding claim 21, Figs 1, 6, 19A-19C, 20A-20C of Yeong discloses a semiconductor device comprising:
a first stack of nanostructures (56A in 50N; Figs 6/19A; ¶ [0058]) over a substrate (50; Fig 19A; ¶ [0014]);
a first gate structure (104/102; Fig 19A; ¶ [0060]) around the first stack of nanostructures;
a first source/drain material (88 in 50N/82; Figs 6/19A; ¶ [0064]) on a first nanostructure of the first stack of nanostructures;
a second source/drain region (88 in 50P/82; Figs 6/19A; ¶ [0064]) on a second nanostructure of the first stack of nanostructures;
a silicide layer (108; Fig 19A; ¶ [0064]) over the substrate, wherein the first source/drain region (88 in 50N; Figs 6/19A; ¶ [0064]) and the second source/drain region (88 in 50P; Figs 6/19A; ¶ [0064]) are separated; and
an isolation layer (60; Fig 19A; ¶ [0014]) between the silicide layer (108; Fig 19A; ¶ [0064]) and the substrate (50; Fig 19A; ¶ [0014]).
Regarding claim 22, Figs 1, 6, 19A-19C, 20A-20C of Yeong discloses the silicide layer (108; Fig 19A; ¶ [0064]) is separated from the first nanostructure (56A in 50N; Figs 6/19A; ¶ [0058]) of the first stack of nanostructures by the first source/drain material (88 in 50N/82; Figs 6/19A; ¶ [0064]).
Allowable Subject Matter
Claims 3-4, 10, 12-13, 23-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the material layer between the silicide layer and the isolation layer, wherein the material layer is in contact with the silicide layer and the isolation layer”.
Regarding claim 10, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the material layer has a higher germanium concentration than the first source/drain region and the second source/drain region”.
Regarding claim 12, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “a semiconductor layer between the material layer and the substrate, wherein the material layer is between the first source/drain region and the semiconductor layer and wherein the semiconductor layer comprises a different material from the substrate”.
Regarding claim 13, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “an isolation layer between the material layer and the substrate”.
Regarding claim 23, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the material layer between the silicide layer and the isolation layer”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lai et al (US 11489078)
Feng et al (US 11189617)
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
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