Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 7-8, 10-11,13 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of US20200168724A1; Hsu et al.; (hereinafter “Hsu”) in view of US20060011990A1; Furukawa et al.; (hereinafter “Furukawa”).
Regarding Claim 1, Hsu teaches a method for forming a transistor ([0015], FinFET manufacture), comprising:
forming lightly doped drain (LDD) regions in a substrate on opposite sides of an active region ([0033], formation of LDD regions can be performed on exposed portions of fins #52, Figure 8B, in substrate #50);
forming a gate stack (Figure 8B) upon the substrate, the gate stack including a gate dielectric layer (#60) and a dummy gate (72) upon the gate dielectric layer;
forming a gate spacer (#86, Figure 9B) on sidewalls of the gate stack;
etching S/D trench within each LDD region to form S/D regions (Figures 10B-12B, recesses #81 are etched in exposed fins #52 to form S/D regions #82); and
forming a strained source and drain (SSD) structure within each S/D trench (Figures 10B-13B, S/D regions #82 is formed to apply strain to channel region #58, [0038]), wherein the SSD structures (#82) do not extend below the gate spacers (#86).
Hsu does not explicitly teach forming the gate stack and the gate spacer overlap the LDD regions, and etching a plurality of S/D trenches within each LDD region.
However, Furukawa teaches a fabrication of a comparable transistor structure (Figure 9), comprising forming a gate stack (#33, device structure) and a gate spacer (#24, sidewall spacers) overlap LLD regions (S/D extension #20/22 of doped S/D regions #28/30), and etching a plurality of S/D trenches (#42/44, Figure 4, trenches) within each LDD region (#28/30).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Hsu with the teaching of Furukawa in order to incorporate multiple volume-expanded features in doped source/drain regions that effectively enhance operating performance by enhancing carrier mobility in the channel region according to Furukawa, [0035].
Regarding Claim 2, Hsu in view of Furukawa teaches the method for forming the transistor as described in claim 1, Hsu further teaches each SSD structure has a dopant gradient concentration that increases from a perimeter towards a center of the SSD structure (Figure 12B, [0042] & [0045], S/D #82 has dopant concentration of layer #82B higher than layer #82A).
Regarding Claim 3, Hsu in view of Furukawa teaches the method for forming the transistor as described in claim 2, Hsu further teaches the dopant concentration at the perimeter of the SSD structure is from about 1×1019 to about 5×1020 atoms/cc ([0042], layer #82A dopant concentration ranges from 5×1019 to 2×1021 atoms/cm3).
Regarding Claim 4, Hsu in view of Furukawa teaches the method for forming the transistor as described in claim 2, Hsu further teaches the dopant concentration at the center of the SSD structure is from about 5×1020 to about 5×1021 atoms/cc ([0045], layer #82B dopant concentration ranges from 1×1020 to 2×1021 atoms/cm3).
Regarding Claim 5, Hsu in view of Furukawa teaches the method for forming the transistor as described in claim 1, Hsu further teaches each SSD structure comprises SiP or SiGe ([0037-0038], S/D #82 comprise SiP or SiGe).
Regarding Claim 7, Hsu in view of Furukawa teaches the method for forming the transistor as described in claim 1, Hsu further teaches each SSD structure has a width of about 10 nm to about 100 nm ([0054], S/D #82 has a thickness of about 40-80 nm).
Regarding Claim 8, Hsu in view of Furukawa teaches the method for forming the transistor as described in claim 1, Hsu further teaches a spacing width of about 10 nm to about 100 nm is present between adjacent SSD structures (Figure 13B, [0054], S/D #82 are separated by fins #52, in which #52 has a width #W1 of about 15nm due to 1:1 ratio with distance #L2, hence spacing between adjacent #82 is at least 15nm or greater).
Regarding Claim 10, Hsu in view of Furukawa teaches the method for forming the transistor as described in claim 1, Hsu further teaches prior to forming the LDD regions, forming an isolation region in the substrate to define the active region (Figures 4-6, [0020], isolation regions #54/#56 are formed prior to LDD regions formation described in [0033]).
Regarding Claim 11, Hsu in view of Furukawa teaches the method for forming the transistor as described in claim 1, Hsu further teaches prior to forming the gate spacer, forming at least one sealing layer upon the sidewalls of the gate stack (Figures 8B-9B, seal spacers #80 are formed before gate spacer #86).
Regarding Claim 13, Hsu in view of Furukawa teaches the method for forming the transistor as described in claim 1, Hsu further teaches after forming the SSD structures (#82, Figure 17B):
removing the dummy gate (#72, Figure 20B) to form a gate volume;
depositing a gate material into the gate volume to form a gate structure (#94, Figures 21B-C);
applying an interlayer dielectric material (#88, Figure 18B) over the S/D regions;
forming a first insulating layer (#108, Figure 22B) over the active region;
etching openings (#110/#112, Figure 23B) through the first insulating layer (#108) to the S/D regions (#82) and the gate structure (#94); and
filling the openings with an electrically conductive material to form at least one source via, at least one drain via, and a gate via ([0060], openings #110/#112 are filled with conductive material to form contact structures).
Regarding Claim 18, Hsu teaches a transistor ([0015], FinFET), comprising:
a substrate (#50, Figure 23B,) comprising a fin (#52) that extends between two S/D regions (#82);
a gate dielectric layer (#92) upon at least three sides of the fin (#52, Figure 1, [0013]) between the two S/D regions;
a gate electrode layer (#94) upon the gate dielectric layer;
a gate spacer (#86, Figure 21C or 23B) on sidewalls of the gate electrode layer;
lightly doped drain (LDD) regions ([0033], formation of LDD regions can be performed on exposed fins #52, Figure 6 or 8A); and
source and drain (SSD) structures (S/D regions #82 is formed to apply strain to channel region #58, [0038]), wherein the SSD structures (#82, Figure 23B) do not extend below the gate spacers (#86).
Hsu does not explicitly teach the LDD regions extending from each S/D region to below the gate dielectric layer and a plurality of SSD structures within each LDD region.
However, Furukawa teaches a comparable transistor structure (Figure 9), comprising LDD regions (#20-22, [0022], S/D extension) extending from each S/D region (#28/#30, source/drain regions) to below gate dielectric layer ([0022], doped S/D regions #28/30 comprise extensions #20/22 extending under gate dielectric #16) and a plurality of SSD structures ([0031], plugs #46 comprise SiGe exerting compressive stress to channel region #32) within each LDD region (#28/30).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Hsu with the teaching of Furukawa in order to incorporate multiple volume-expanded features in source/drain regions that effectively enhance operating performance by enhancing carrier mobility in the channel region according to Furukawa, [0035].
Regarding Claim 19, Hsu in view of Furukawa teaches the transistor as described in claim 18, wherein Hsu further teaches a spacing width of about 10 nm to about 100 nm is present between adjacent SSD structures (Figure 13B, [0054], S/D #82 are separated by fins #52, in which #52 has a width #W1 of about 15nm due to 1:1 ratio with distance #L2, hence spacing between adjacent #82 is at least 15nm or greater).
Regarding Claim 20, Hsu in view of Furukawa teaches the transistor as described in claim 18, wherein Hsu further teaches each SSD structure has a dopant gradient concentration that increases from a perimeter towards a center of the SSD structure ([0042] & [0045], S/D regions #82 has dopant concentration of layer #82B higher than layer #82A).
Claims 6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Furukawa, and further in view of US20180166575A1; Colinge et al.; (hereinafter “Colinge”).
Regarding Claim 6, Hsu in view of Furukawa teaches the method for forming the transistor as described in claim 1.
Hsu in view of Furukawa does not explicitly teach the gate spacer has a width of about 10 nm to about 100 nm.
However, Colinge teaches a method for manufacturing a comparable FinFET structure (Figure 1A, [0021]), wherein the gate spacer has a width of about 10 nm to about 100 nm (Figure 2C, [0036], spacer #125 is about 10nm).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to have selected the ranges disclosed by Colinge in order to provide sufficient protection to gate structure according to Colinge, [0036].
Regarding Claim 12, Hsu in view of Furukawa teaches the method for forming the transistor as described in claim 11.
Hsu in view of Furukawa does not explicitly teach each sealing layer has a width of about 10 nm to about 100 nm.
However, Colinge teaches each sealing layer has a width of about 10nm to about 100 nm ([0036], offset spacer #116 can have a width of about 10 nm).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to have selected the ranges disclosed by Colinge in order to provide sufficient protection to gate structure according to Colinge, [0036].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Furukawa, and further in view of US20150303302A1; Yu et al.; (hereinafter “Yu”).
Regarding Claim 9 (currently amended), Hsu in view of Furukawa teaches the method for forming the transistor as described in claim 1, Hsu further teaches each S/D trench has a cross-section with a smaller width at a bottom of the S/D trench (Figure 10B, recesses #81 has a smaller width at the bottom).
Hsu in view of Furukawa does not explicitly teach each S/D trench has a trapezoidal cross-section.
However, Yu teaches a method of manufacturing a semiconductor device (Figures 1-11, [0021]), wherein each S/D trench has a trapezoidal cross-section (Figure 8, [0025], opening #218 has a convex quadrilateral shape).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Hsu in view of Furukawa with the teaching of Yu, as it would be a simple substitution of one known element (recess profile of Hsu) for another (recess profile of Yu) to obtain predictable results. See MPEP 2143(I)(B).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Furukawa, and further in view of US20220328657A1; Lu et al.; (hereinafter “Lu”).
Regarding Claim 14, Hsu in view of Furukawa teaches the method for forming the transistor as described in claim 13.
Hsu in view of Furukawa does not explicitly teach forming a second insulating layer over the first insulating layer; etching the second insulating layer to form pads over the vias; and filling the pads with an electrically conductive material to form a source electrode, a drain electrode, and a gate electrode.
However, Lu teaches a method of manufacturing a transistor device ([0010]), comprising: forming a second insulating layer (#254, Figure 19, dielectric layer) over a first insulating layer (#253, dielectric layer); etching the second insulating layer to form pads (#252L, metal lines) over the vias (#252V, conductive vias); and filling the pads with an electrically conductive material to form a source electrode, a drain electrode, and a gate electrode ([0068-0070], #252L and #252V form of metal materials).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Hsu in view of Furukawa with the teaching of Lu in order to provide horizontal interconnections in the metallization layer to the source/drain structures according to Lu, [0068-0069].
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of US20190245087A1; Tsai et al; (hereinafter “Tsai”) and Furukawa.
Regarding Claim 15 (currently amended), Hsu teaches a transistor ([0015], FinFET), comprising:
a substrate (#50, Figure 23B,);
a gate stack (Figure 21C) upon the substrate that includes a gate dielectric layer (#60) and a gate structure (#94) upon the gate dielectric layer;
a first lightly doped drain (LDD) region and a second LDD region, ([0033], formation of LDD regions can be performed on exposed portion of fins #52, Figure 8B (not explicitly shown));
a gate spacer (#86, Figure 23B) on sidewalls of the gate stack; and
strained source and drain (SSD) structures (S/D regions #82 is formed to apply strain to channel region #58, [0038]), wherein the SSD structures (#82) do not extend below the gate spacers (#86);
wherein the SSD structures are in the form of a trench having a necking profile with a smaller width at a bottom of the trench than at a top of the trench (Figure 10B or 23B, S/D regions #82 form in recess #81 having a smaller width at the bottom); and
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wherein each SSD structure has a dopant gradient concentration that increases from a perimeter towards a center of the SSD structure ([0042] & [0045], S/D regions #82 has dopant concentration of layer #82B higher than layer #82A).
Hsu does not explicitly teach the first LDD region and the second LDD region extend away from below the gate stack towards opposite sides of the gate stack, the first and second LDD regions being located proximate an upper surface of the substrate; and each SSD structure passes through the LDD region and extends into the substrate below the LDD region.
However, Tsai teaches a fabrication of a comparable FinFET structure ([0021]), comprising a first LDD region and a second LDD region extend away from below a gate stack towards opposite sides of the gate stack (Figure 5B of Tsai annotated, LDD features #128 extends below gate stack #120 toward opposite sides of #120), the first and second LDD regions being located proximate an upper surface of the substrate (#128 disposes on upper surface of substrate #110); and each SSD structure (#138, [0043], S/D features for providing tensile stress to channel region) passes through the LDD region (#128) and extends into the substrate (#110) below the LDD region.
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Hsu with the teaching of Tsai, as it would be a simple substitution of one known element (configuration of LDD regions and S/D feature of Hsu) for another (configuration of LDD regions and S/D feature of Tsai) in comparable structures to obtain predictable results. See MPEP 2143(I)(B).
Hsu in of Tsai does not explicitly teach a plurality of strained source and drain (SSD) structures within each LDD region.
However, Furukawa teaches a comparable transistor structure (Figure 9), comprising a plurality of SSD structures ([0031], plugs #46 comprise SiGe material exerting compressive stress to channel region #32) within each LDD region (#28/30, doped source/drain regions).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Hsu in view of Tsai with the teaching of Furukawa in order to incorporate multiple volume-expanded features in doped source/drain regions that effectively enhance operating performance by enhancing carrier mobility in the channel region according to Furukawa, [0035].
Regarding Claim 17 (currently amended), Hsu in view of Furukawa teaches the transistor as described in claim 15, wherein Hsu further teaches each SSD structure also has a capping portion above the substrate (Figure 23B, [0054], S/D regions #82 comprises a cap layer #82E above substrate #50).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Tsai and Furukawa, and further in view of US20160254365A1; Yu et al.; (hereinafter “Yu-365”).
Regarding Claim 16 (currently amended), Hsu in view of Tsai and Furukawa teaches the transistor as described in claim 15, wherein Hsu further teaches a first sealing layer upon the sidewalls of the gate stack, located between the gate stack and the gate spacer.
Hsu in view of Tsai and Furukawa does not teach a second sealing layer upon the sidewalls of the gate stack, located between the gate stack and the gate spacer.
However, Yu-365 teaches a FinFET device ([0014]) comprising a second sealing layer (#318, Figure 3J, seal spacers) upon the sidewalls of gate stack (#310, gate structure), located between the gate stack (#310) and gate spacer (#320).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Hsu in view of Tsai and Furukawa with the teaching of Yu-365 in order to further provide protection for the vertical sides of the gate structure according to Yu-365, [0022].
Response to Arguments/Amendments
Applicant's amendments to the abstract and the specification, page 7 of the remarks, filed 06/18/2026, with respect to objections of the abstract and specification have been fully considered. Accordingly, the objections have been withdrawn.
Applicant's amendments to claim 9, page 7 of the remarks, with respect to claim objection has been fully considered. Accordingly, the objection has been withdrawn.
Applicant's arguments to claim 1, page 7 of the remarks, with respect to 35 U.S.C 103 rejections of claim 1 as unpatentable over Hsu in view of Tsai have been fully considered.
Applicant argues in page 7 of the remarks that Office Action, filed 03/19/2026, does not show Tsai to disclose the gate stack overlapping the LDD regions. However, examiner respectfully disagrees. Figure 2 or 5B annotated of Tsai provides a clear teaching of the gate stack (#120) having an overlap portion with LDD region (#128).
Applicant further argues in page 7 of the remarks that Hsu fails to teach etching a plurality of S/D trenches in each LDD region. The argument is found persuasive. Hence, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103 as being unpatentable over Hsu in view of Furukawa. (see 35 U.S.C. 103 rejection of claims 1 above).
Applicant's amendments to claim 15 and corresponding arguments, pages 8 of the remarks, with respect to 35 U.S.C 103 rejection of claim 15 as unpatentable over Hsu in view of Furukawa have been fully considered.
Applicant argues in page 8 of the remarks that Office Action, filed 03/19/2026, does not show Furukawa to disclose the LDDs regions extend under the gate stack. However, examiner respectfully disagrees. Figures 8-9 of Furukawa provide a clear teaching of the S/D extensions #20/22 of the doped S/D regions #28/30 extending under the gate stack #33, including gate electrode #18, spacers #24 and dielectric #16.
Applicant further argues in page 8 of the remarks that Furukawa fails to teach the limitation “each SSD structure passes through the LDD region and extends into the substrate below the LDD region” as recited in amended claim 15. The argument is persuasive. Hence, the rejection to claim 15 has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103 as being unpatentable over Hsu in view of Tsai and Furukawa. Tsai has been introduced in view of the amendments to claim 15 (see 35 U.S.C. 103 rejection of claims 15 above).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20150179795A1 – Figures 1-3 and [0058] & [0064-0065]
US20070210301A1 – Figures 5-6 and [0049-0050]
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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