DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed 5/8/2026.
Claims 1-15 and 21-25 are pending. Claims 16-20 are cancelled. Claims 21-25 are new. Claims 1, 10 and 21 are independent.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/19/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 5/8/2026 is acknowledged.
Claims 16-20, which have been canceled, were drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/8/2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed subject matter of claims 10 and 21 must be shown or the feature(s) canceled from the claim(s). For example, claim 10 recites the limitation “depositing a dielectric layer over a metallization layer, wherein the dielectric layer has a conductive feature therein; etching a well in the dielectric layer to expose the conductive feature” (emphasis added) and claim 21 recites the limitation “forming a first patterned metallization layer; forming a dielectric layer on the patterned metallization layer, the dielectric layer having a well aligned with a first conductive feature formed within the dielectric layer” (emphasis added), which do not appear to be shown in the Drawings of the current application. As shown in Figures 3A-3C of the Drawings of the current application the dielectric layer 103 is formed over metallization layer 101 which includes a conductive feature 102 formed within the metallization layer 101 not the dielectric layer 103. Then an opening 1001 is formed in the dielectric layer 103 to expose the conductive feature 102 within the metallization layer 101. The Drawings of the current application do not show the conductive feature being formed within the dielectric layer. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1, 3-6, 9, 15, 23 and 25 are objected to because of the following informalities:
Claim 1 recites the limitation “an openings” in line 5 of the claim, which appear to be grammatically incorrect, and thus the Examiner suggests amending the limitation to remove the term “an”.
Claim 3 recites the limitation “the RRAM stack” in line 1 of the claim, which the Examiner suggests amending to “the RRAM layer stack”, because it appears the claimed element was originally introduced using that specific language.
Claim 4 recites the limitation “the RRAM stack” in line 1 of the claim, which the Examiner suggests amending to “the RRAM layer stack”, because it appears the claimed element was originally introduced using that specific language.
Claim 5 recites the limitation “the RRAM stack” in line 1 of the claim, which the Examiner suggests amending to “the RRAM layer stack”, because it appears the claimed element was originally introduced using that specific language.
Claim 6 recites the limitation “the RRAM stack” in line 1 of the claim, which the Examiner suggests amending to “the RRAM layer stack”, because it appears the claimed element was originally introduced using that specific language.
Claim 9 recites the limitation “the ELK material” in line 2 of the claim, which the Examiner suggests amending to “the ELK dielectric material”, because it appears the claimed element was originally introduced using that specific language.
Claim 15 recites the limitation “the ELK material” in line 2 of the claim, which the Examiner suggests amending to “the ELK dielectric material”, because it appears the claimed element was originally introduced using that specific language.
Claim 23 recites the limitation “the bottom electrode” in line 2 of the claim, which the Examiner suggests amending to “the bottom electrode layer”, because it appears the claimed element was originally introduced using that specific language.
claimed element was originally introduced using that specific language.
Claim 23 recites the limitation “TaNor” in line 3 of the claim, which appears to be a typographical error, and thus the Examiner suggests amending to “TaN or”.
Claim 23 recites the limitation “the top electrode” in line 5 of the claim, which the Examiner suggests amending to “the top electrode layer”, because it appears the claimed element was originally introduced using that specific language.
Claim 25 recites the limitation “the ELK material” in line 2 of the claim, which the Examiner suggests amending to “the ELK dielectric material”, because it appears the claimed element was originally introduced using that specific language.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 10-15 and 21-25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 10 recites the limitation “depositing a dielectric layer over a metallization layer, wherein the dielectric layer has a conductive feature therein; etching a well in the dielectric layer to expose the conductive feature” (emphasis added) in lines 2-4 of the claim and claim 21 recites the limitation “forming a first patterned metallization layer; forming a dielectric layer on the patterned metallization layer, the dielectric layer having a well aligned with a first conductive feature formed within the dielectric layer” (emphasis added) in lines 2-4 of the claim, which do not appear to be supported by the originally filed Specification of the current application. As disclosed in paragraphs [0037]-[0039] of the Specification and in association with Figures 3A-3C of the Drawings of the current application the dielectric layer 103 is formed over metallization layer 101 which includes a conductive feature 102 formed within the metallization layer 101 not the dielectric layer 103. Then an opening 1001 is formed in the dielectric layer 103 to expose the conductive feature 102 within the metallization layer 101. Thus, the originally filed disclosure does contain support for the conductive feature being formed within the dielectric layer as recited in the limitations of claims 10 and 21.
For the purposes of prosecution, the limitations in question in claims 10 and 21 will be interpreted by the embodiment supported within the originally filed disclosure, specifically with the claimed “conductive feature” being formed within the “metallization layer” not the “dielectric layer”.
Note the dependent claims 11-15 and 22-25 do not cure the deficiencies of the claims on which they depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-8, 10-15 and 21-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation “the RRAM stack bottom electrode layer material” in lines 1-2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation “the resistance switch layer material” in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation “the top electrode layer material” in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation “the RRAM stack bottom electrode layer material thickness” in lines 1-2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation “the resistance switch layer material thickness” in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation “the top electrode layer material thickness” in lines 3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation “the dielectric layer well top width” in lines 12-13 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation “the well first sidewall” in line 14 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation “the well second sidewall” in line 14 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation “the ILD second conductive feature” in lines 21-22 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation “the bottom electrode layer material thickness” in lines 1-2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation “the resistance switch layer material thickness” in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation “the top electrode layer material thickness” in lines 2-3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 15 recites the limitation “the ILD material” in line 1 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 21 recites the limitation “the dielectric layer well” in line 9 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 21 recites the limitation “the dielectric layer well top width” in line 11 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 21 recites the limitation “the well first sidewall” in line 12 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 21 recites the limitation “the well second sidewall” in line 13 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 21 recites the limitation “the well second sidewall” in line 13 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 22 recites the limitation “the RRAM cell bottom electrode layer material” in lines 1-2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 22 recites the limitation “the resistance switch layer material” in lines 2-3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 22 recites the limitation “the top electrode layer material” in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Note the dependent claims 11-15 and 21-25 necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6-7, 9, 21 and 24-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiu et al. (US 2022/0102428 A1, hereinafter “Chiu”).
Regarding independent claim 1, Chiu discloses a method of fabricating a resistive random-access memory (RRAM) structure, the method comprising:
forming a first patterned metallization layer 110 (“metal/dielectric layers”- ¶0013) (see Fig. 1);
disposing a dielectric layer 120 (“dielectric layer”- ¶0015) on the first patterned metallization layer 110 (see Fig. 2);
etching an openings 120O (“opening”- ¶0016, which includes a plurality of openings 120O- see Fig. 9) exposing first contact portions 112 (“conductive feature”- ¶0016, which includes a plurality of first contact portions 112- see Fig. 9) of the first patterned metallization layer 110, each opening 120O having an annular tapered sidewall tapering inward to a corresponding one of the first contact portions 112 (¶0016) (see Fig. 3);
disposing a RRAM layer stack over the dielectric layer 120 and conformally in the openings 120O, the RRAM layer stack including a first conductive electrode layer 130 (“bottom electrode layer”- ¶0019), a resistance switch layer 140 (“resistance switch layer”- ¶0019) disposed on the first conductive electrode layer 130, and a second conductive electrode layer 150 (“top electrode layer”- ¶0019) disposed on the resistance switch layer 140 (see Fig. 4);
etching the RRAM layer stack to form mutually isolated RRAM cells MS1 (“memory structure”- ¶0032, which includes a plurality of RRAM cells MS1- see Fig. 9), each RRAM cell MS1 comprising a portion of the RRAM layer stack remaining after the etching and disposed entirely inside a corresponding opening 120O (¶¶0028-0033) (see Figs. 5-7);
disposing an interlayer dielectric (ILD) material 180 (“inter-layer dielectric layer”- ¶0046) over the dielectric layer 120 and over the RRAM cells MS1 (see Fig. 8);
forming conductive vias 190 (“conductive feature”- ¶0035, which includes a plurality of conductive features 190- see Fig. 9, specifically the “conductive via” portion of 190, which is the bottom portion of 190- ¶0035) passing through the ILD material 180 and contacting the RRAM cells MS1 (see Fig. 8); and
forming a second patterned metallization layer 190 (“conductive feature”- ¶0035, specifically the “metal line” portion of 190, which is the top portion of 190- ¶0035) on the ILD material 180 and electrical connecting with the conductive vias 190 (see Fig. 8).
Regarding claim 2, Chiu discloses the method further comprising:
prior to forming the first patterned metallization layer 110, forming a transistor layer comprising a plurality of transistors 912 (“transistors”- ¶0037) (see Fig. 9);
wherein the first metallization layer 110 electrically connects the first contact portions 112 of the first patterned metallization layer 110 with the transistors 912 of the transistor layer (¶0037) (see Fig. 9).
Regarding claim 6, Chiu discloses wherein the RRAM stack is located within the openings 120O to reduce an overall step height associated with the RRAM cell MS1, as compared to the RRAM cell being located on a top surface of the dielectric layer 120 (see Figs. 4-7).
Regarding claim 7, Chiu discloses wherein the RRAM stack bottom electrode layer 130 material is one of TiN, TaN, Ta, Ru, W or Mo (¶0021); the resistance switch layer 140 material is one HfOTaO, AlO, ZrO, HfZrO, or AITaO (¶0022); and the top electrode layer 150 material is one of TiN, TaN, Ta, Ru, W or Mo (¶0025).
Regarding claim 9, Chiu discloses wherein the ILD 180 material is an extra-low-k (ELK) dielectric material, and the ELK material is one or more of silicon oxide and carbon-doped silicon oxide (¶0034).
Regarding independent claim 21, Chiu discloses a method of forming a semiconductor memory structure comprising:
forming a first patterned metallization layer 110 (“metal/dielectric layers”- ¶0013) (see Fig. 1);
forming a dielectric layer 120 (“dielectric layer”- ¶0015) on the patterned metallization layer 110, the dielectric layer 120 having a well 120O (“opening”- ¶0016) aligned with a first conductive feature 112 (“conductive feature”- ¶0016) formed within the dielectric layer 120, and the well 120O defined by a bottom, a top, a bottom width, a top width greater than the bottom width, a tapered first sidewall extending from the bottom to the top, and a tapered second sidewall extending from the bottom to the top (see Fig. 3);
forming a resistive random-access memory (RRAM) cell cells MS1 (“memory structure”- ¶0032) on the dielectric layer 120 and aligned with the dielectric layer well 120O, the RRAM cell MS1 including a bottom electrode layer 130 (“bottom electrode layer”- ¶0019), a resistance switch layer 140 (“resistance switch layer”- ¶0019) and a top electrode layer 150 (“top electrode layer”- ¶0019), and the RRAM cell MS1 defined by a cell width which is less than the dielectric layer well 120O top width, wherein the RRAM cell MS1 is located within the well 120O and extends to a first portion of the well first sidewall and extends to a first portion of the well second sidewall, and the well first sidewall and the well second sidewall each have a respective second portion that is free of any contact with the RRAM cell MS1 (¶¶0028-0033) (see Figs. 5-7);
forming an interlayer dielectric (ILD) layer 180 (“inter-layer dielectric layer”- ¶0046, including the “via” portion of 190) on the RRAM cell MS1, the IML including a via 190 (“conductive feature”- ¶0035, specifically the “conductive via” portion of 190, which is the bottom portion of 190- ¶0035) connected to the RRAM cell MS1 (see Fig. 8); and
forming a metallization layer 190 (“conductive feature”- ¶0035, specifically the “metal line” portion of 190, which is the top portion of 190- ¶0035) including an embedded second conductive feature connected to the via 190 (see Fig. 8).
Regarding claim 24, Chiu discloses the method further comprising forming a hard mask layer 160 (“hard mask layer”- ¶0019) on the top electrode layer 150 (see Fig. 4), wherein the via 190 is formed to extend into the top electrode layer 150 and the hard mask layer 160 (see Fig. 8).
Regarding claim 25, Chiu discloses wherein the ILD layer 180 is formed of an extra- low-k (ELK) dielectric material, and the ELK material is one or more of silicon oxide and carbon-doped silicon oxide (¶0034).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3-5, 8 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable and obvious over Chiu.
Regarding claim 3, Chiu discloses wherein the RRAM stack has a width (i.e., the bottom width of the RRAM layer stack which is equivalent to L1- see Fig. 3-4), which is “about 50 nanometers to about 500 nanometers” (¶0018), which overlaps the claimed range of “85nm or less”. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)).
Regarding claim 4, Chiu discloses wherein the RRAM stack has a width (i.e., the bottom width of the RRAM layer stack which is equivalent to L1- see Fig. 3-4), which is “about 50 nanometers to about 500 nanometers” (¶0018), which overlaps the claimed range of “75nm or less”. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)).
Regarding claim 5, Chiu discloses wherein the RRAM stack has a width (i.e., the bottom width of the RRAM layer stack which is equivalent to L1- see Fig. 3-4), which is “about 50 nanometers to about 500 nanometers” (¶0018), which overlaps the claimed range of “65nm or less”. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)).
Regarding claim 8, Chiu discloses wherein the bottom electrode layer 130, the resistance switch layer 140 and the top electrode layer 150 have respective thicknesses (see Fig. 4).
Chiu does not expressly disclose wherein the RRAM stack bottom electrode layer material thickness is 80-150A; the resistance switch layer material thickness is 20-30A; and the top electrode layer material thickness is 100-250A.
However, it would have been obvious to form the thicknesses of the bottom electrode layer, the resistance switch layer and the top electrode layer within the claimed ranges, respectively, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 22, Chiu discloses wherein the RRAM cell bottom electrode layer 130 material is formed to have a thickness; the resistance switch layer 140 material is formed to have a thickness; and the top electrode layer 150 material is formed to have a thickness (see Fig. 4).
Chiu does not expressly disclose wherein the RRAM cell bottom electrode layer material is formed to have a thickness of 80-150A; the resistance switch layer material is formed to have a thickness of 20-30A; and the top electrode layer material is formed to have a thickness of 100-250A.
However, it would have been obvious to form the thicknesses of the bottom electrode layer, the resistance switch layer and the top electrode layer within the claimed ranges, respectively, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 23, Chiu discloses the method further comprising:
forming a barrier layer (i.e., “diffusion barrier layer”- ¶0020) between the bottom electrode (i.e., “electrode layers”- ¶0020) and the dielectric layer 120, the barrier layer formed of one of TiN, TaNor Ta (¶0021), and the barrier layer formed to have a thickness; and
forming a hard mask layer 160 (“hard mask layer”- ¶0019) on the top electrode 150, the hard mask layer 160 formed of one of SiON or SiN (¶0026), and the hard mask layer 160 formed to have a thickness (see Fig. 4).
Chiu does not expressly disclose wherein the barrier layer formed to have a thickness of 80-150A and the hard mask layer formed to have a thickness of 100-200A.
However, it would have been obvious to form the thicknesses of the barrier layer and hard mask layer within the claimed ranges, respectively, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Claims 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu in view of Chou (US 2020/0075857 A1).
Regarding independent claim 10, Chiu discloses a method of fabricating a semiconductor memory structure comprising:
depositing a dielectric layer 120 (“dielectric layer”- ¶0015) over a metallization layer 110 (“metal/dielectric layers”- ¶0013), wherein the dielectric layer 120 has a conductive feature 112 (“conductive feature”- ¶0014) therein (see Fig. 2);
etching a well 120O (“opening”- ¶0016) in the dielectric layer 120 to expose the conductive feature 112, such that the dielectric layer well 120O is defined by a bottom, a top, a bottom width, a top width greater than the bottom width, a tapered first sidewall extending from the bottom to the top, and a tapered second sidewall extending from the bottom to the top (¶0016) (see Fig. 3);
depositing a bottom electrode layer 130 (“bottom electrode layer”- ¶0019) into the well 120O (see Fig. 4);
depositing a resistance switch layer 140 (“resistance switch layer”- ¶0019) over the bottom electrode layer 130 (see Fig. 4);
depositing a top electrode layer 150 (“top electrode layer”- ¶0019) over the resistance switch layer 140 (see Fig. 4);
patterning the bottom electrode layer 130, the resistance switch layer 140 and the top electrode layer 150 into a resistance switch cell MS1 (“memory structure”- ¶0032) defined by a cell width which is less than the dielectric layer well 120O top width, such that the resistance switch cell MS1 is located within the well 120O and extends to a first portion of the well first sidewall and extends to a first portion of the well second sidewall wall, and the well first sidewall wall and the well second sidewall each have a respective second portion that is free of any contact with the resistance switch cell MS1 (¶¶0028-0033) (see Figs. 5-7);
depositing an interlayer dielectric (ILD) layer 180 (“inter-layer dielectric layer”- ¶0046) over the resistance switch cell MS1 (see Fig. 8);
forming a via 190 (“conductive feature”- ¶0035, specifically the “conductive via” portion of 190, which is the bottom portion of 190- ¶0035) in the ILD 180, the via 190 connected to the resistance switch cell MS1 (see Fig. 8);
forming a second conductive feature 190 (“conductive feature”- ¶0035, specifically the “metal line” portion of 190, which is the top portion of 190- ¶0035) in the ILD 180, the second conductive feature 190 connected to the via 190 (see Fig. 8); and
wherein further metallization layers can be formed (¶0037).
Chiu does not expressly disclose forming a metallization layer over the ILD, the metallization layer connected to the ILD second conductive feature.
Chou discloses a method of fabricating a semiconductor memory structure comprising forming a depositing an interlayer dielectric (ILD) layer 126/130 (collectively 126 “IMD layer” and 130 “ILD layer”- ¶¶0018, 0020) over a resistance switch cell 122 (“memory cell”- ¶0016), forming a via 132 (“via”- ¶0020) in the ILD 126/30, the via 132 connected to the resistance switch cell 122, forming a second conductive feature 134 (“conductive wire”- ¶0020) in the ILD 126/130, the second conductive feature 134 connected to the via 132, and forming a metallization layer (i.e., “overlying metal layers”- ¶0029) over the ILD 126/130, the metallization layer connected to the ILD second conductive feature 134 (¶0029) (see Fig. 8-12).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Chiu such that it further comprises forming a metallization layer over the ILD, the metallization layer connected to the ILD second conductive feature as taught by Chou for the purpose of forming a suitable and well-known metallization layer and associated configuration to connect the resistance switch cell to other components in the device such as the bit line (Chou ¶0029).
Regarding claim 11, Chiu discloses wherein the resistance switch cell MS1 has a width (i.e., the bottom width of the RRAM layer stack which is equivalent to L1- see Fig. 3-4) of “about 50 nanometers to about 500 nanometers” (¶0018), which overlaps the claimed range of “85nm or less”, and the resistance switch cell MS1 width is less than the well 120O top width (see Fig. 7). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)).
Regarding claim 12, Chiu discloses wherein the resistance switch cell MS1 has a width (i.e., the bottom width of the RRAM layer stack which is equivalent to L1- see Fig. 3-4) of “about 50 nanometers to about 500 nanometers” (¶0018), which overlaps the claimed range of “75nm or less”, and the resistance switch cell MS1 width is less than the well 120O top width (see Fig. 7). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)).
Regarding claim 13, Chiu discloses wherein the resistance switch cell MS1 has a width (i.e., the bottom width of the RRAM layer stack which is equivalent to L1- see Fig. 3-4) of “about 50 nanometers to about 500 nanometers” (¶0018), which overlaps the claimed range of “65nm or less”, and the resistance switch cell MS1 width is less than the well 120O top width (see Fig. 7). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists (In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976)).
Regarding claim 14, Chiu discloses wherein the bottom electrode layer 130, the resistance switch layer 140 and the top electrode layer 150 have respective thicknesses (see Fig. 4).
Chiu does not expressly disclose wherein the bottom electrode layer material thickness is 80-150A; the resistance switch layer material thickness is 20-30A; and the top electrode layer material thickness is 100-250A.
However, it would have been obvious to form the thicknesses of the bottom electrode layer, the resistance switch layer and the top electrode layer within the claimed ranges, respectively, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 15, Chiu discloses wherein the ILD 180 material is an extra-low-k (ELK) dielectric material, and the ELK material is one or more of silicon oxide and carbon-doped silicon oxide (¶0034).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Banno et al. (US 2016/0359110 A1), which discloses a method of fabricating a semiconductor memory structure comprising forming an opening with tapered sidewalls in a dielectric layer.
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/JAY C CHANG/Primary Examiner, Art Unit 2817
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