DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Invention I, Species A directed to Fig. 10 (Claims 1-3, 5-6, 11-15 and 17) in the reply filed on April 29th, 2026 is acknowledged.
Applicant's election with traverse of Invention I, Species A directed to Fig. 10 (Claims 1-3, 5-6, 11-15 and 17) in the reply filed on April 29th, 2026 is acknowledged. The traversal is on the ground(s) that claim 17 recites a processing step but rather than a structural claim. The Examiner agrees that claim 17 is a method claim, however, the language of the claim is generic and has almost the same limitation of the device claim 1. Therefore, claim 17 is also being grouped together with the device claims for examination.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 17 recites a redundant “a substrate” in line 6 because claim 17 already recites “a substrate” in line 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-7, 9-12, and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Spencer et al. (Patent No.: US 7,871,854 B1), hereinafter as Spencer in view of Chen et al. (Pub. No.: US 2009/0101909 A1), hereinafter as Chen.
Regarding claim 1, Spencer discloses a semiconductor structure in Fig. 17, comprising: a substrate (substrate 62 same as substrate 12) comprising a first semiconductor material (silicon) (see column 2, lines 18-25 and column 4, line 1); a first doped region (left portion of region 82) disposed in the substrate and having a first conductivity type (p type) (see column 4 and lines 17-20); a second doped region (right portion of region 74) disposed in the substrate and separated from the first doped region, the second doped region having a second conductivity type (n type) different than the first conductivity type (see column 4 and lines 37-38); a first epitaxial region (layer 68) disposed in a cavity (opening 66) of the substrate, the first epitaxial region with an impurity of the second conductivity type (n type) (see column 4 and lines 2-10); and a second epitaxial region (layer 88) disposed in the cavity of the substrate and connected to the first epitaxial region, the second epitaxial region comprising a second semiconductor material (germanium) different than the first semiconductor material (see column 4 and lines 46-53).
Spencer fails to disclose the first epitaxial region comprising the first semiconductor material (silicon).
Chen discloses a semiconductor structure comprising a substrate (substrate 302) comprising a first semiconductor material (silicon) and a first region (n-sub 318) comprising the first semiconductor material (silicon) with an impurity of a second conductivity type (n-type) (see Fig. 22 and [0059-0060]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the material of silicon of the first region of Chen (n-sub 318) into the semiconductor structure of Spencer for making the first epitaxial region because the modified structure would provide high performance photodetector with a silicon material for making n-type region and germanium for making p-type region for optimizing light absorption and fast carrier mobility and easier manufacturing with CMOS compatibility.
Regarding claim 2, the combination of Spencer and Chen discloses the semiconductor structure of claim 1, wherein the substrate comprises a first inner sidewall (left sidewall of opening 66) and a second inner sidewall (right sidewall of opening 66) opposite to the first inner sidewall (see Fig. 11 of Spencer), the first epitaxial region is connected to the first inner sidewall (layer 68 connects to left sidewall), and the second epitaxial region is connected to the second inner sidewall (layer 88 electrically connected to right sidewall of opening 66) (see Fig. 17 of Spencer).
Regarding claim 4, the combination of Spencer and Chen discloses the semiconductor structure of claim 1, wherein an upper surface of the second epitaxial region extends past an upper surface of the first epitaxial region (an upper surface of layer 88 is above an upper surface of layer 68) (see Fig. 17 of Spencer).
Regarding claim 5, the combination of Spencer and Chen discloses the semiconductor structure of claim 1, wherein the first epitaxial region (layer 68) is connected (physically contacts) to a first side of the cavity (left sidewall of opening 66) facing the first doped region (left portion of region 82), and the second epitaxial region (layer 88) is connected (electrically connected) to a second side of the cavity (right sidewall of opening 66) facing the second doped region (right portion of region 74) (see Figs. 11 and 17 of Spencer).
Regarding claim 6, the combination of Spencer and Chen discloses the semiconductor structure of claim 1, wherein the substrate comprises an inner sidewall (left sidewall of opening 66) and a lower surface (bottom surface of opening 66) connected to the inner sidewall, the first epitaxial region comprises a first portion (vertical portion of layer 68) lining the inner sidewall (see Figs. 11 and 17 of Spencer) and a second portion (horizontal portion of layer 68) connected to the first portion, and a height of the first portion from the lower surface of the substrate is greater than a height of the second portion from the lower surface of the substrate (see Fig. 17 of Spencer).
Regarding claim 7, the combination of Spencer and Chen discloses the semiconductor structure of claim 1, a capping layer (layer 90) overlying an upper surface of the second epitaxial region (see Spencer, Fig. 17, column 4, lines 46-53).
Regarding claim 9, the combination of Spencer and Chen discloses the semiconductor structure of claim 1, wherein the first and second doped regions, the first and second epitaxial regions, and a portion of the substrate laterally between the first epitaxial region and the first doped region are included in an avalanche photodetector (photodetector device 60) (see Spencer, Fig. 17 and column 4, lines 28-65).
Regarding claim 10, the combination of Spencer and Chen discloses the semiconductor structure of claim 1, wherein the second epitaxial region acts as an absorption region of the avalanche photodetector (layer 88 has p-type acts as absorption region for light), the first epitaxial region acts as a charge region of the avalanche photodetector (layer 68 has n-type acts as charge region), and the portion of the substrate acts as a multiplication region of the avalanche photodetector (substrate 62 act as multiplication region) (see Spencer and Fig. 17).
Regarding claim 11, Spencer discloses a semiconductor structure in Figs. 11 and 17, comprising: a substrate (substrate 62 same as substrate 12) comprising a first inner sidewall (left sidewall of opening 66) and a second inner sidewall (right sidewall of opening 66) opposite to the first inner sidewall (see Fig. 11, column 2, lines 18-25 and column 4, line 1); a first doped region (left portion of region 74 of n type) disposed in the substrate and close to the first inner sidewall (see Fig. 17, column 4 and lines 17-20); a second doped region (right portion of region 82 of p type) disposed in the substrate and close to the second inner wall, the second doped region having different conductivity than the first conductivity type (p type different from n type) (see column 4 and lines 37-38); a first epitaxial region (layer 88) connected to the first inner sidewall of the substrate (electrically connected), the first epitaxial region comprising a first semiconductor material (germanium) having an impurity (p type doping) (see Fig. 17, column 4 and lines 46-53); and a second epitaxial region (layer 68) connected to the second inner sidewall of the substrate (physically connected) and the first epitaxial region (see Fig. 17, column 4 and lines 2-10).
Spencer fails to disclose the second epitaxial region comprising a second semiconductor material has different band gap than the first semiconductor material.
Chen discloses a semiconductor structure comprising a first epitaxial region (layer 342) comprising a first semiconductor material (germanium) and a second region (n-sub 318) comprising a second semiconductor material (silicon) with an impurity of a second conductivity type (n-type) (see Fig. 22 and [0059-0060]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the material of silicon of the second region of Chen (n-sub 318) into the semiconductor structure of Spencer for making the second semiconductor material of the second epitaxial region so that the second epitaxial region comprising the second semiconductor material (silicon) with different band gap than the first semiconductor material (germanium) because the modified structure would provide high performance photodetector with a silicon material for making n-type region and germanium for making p-type region for optimizing light absorption and fast carrier mobility and easier manufacturing with CMOS compatibility.
Regarding claim 12, the combination of Spencer and Chen discloses the semiconductor structure of claim 1, wherein the first doped region comprises n-type dopants (left portion of region 74 of n type), the second doped region comprises p-type dopants (right portion of region 82 of p type), and the first epitaxial region comprises a p-type impurity (layer 88 of p-type) (see Fig. 17 of Spencer).
Note: different interpretation for claim 11 to reject claim 14.
Regarding claim 11, Spencer discloses a semiconductor structure in Figs. 11 and 17, comprising: a substrate (substrate 62 same as substrate 12) comprising a first inner sidewall (left sidewall of opening 66) and a second inner sidewall (right sidewall of opening 66) opposite to the first inner sidewall (see Fig. 11, column 2, lines 18-25 and column 4, line 1); a first doped region (left portion of region 74 of n type) disposed in the substrate and close to the first inner sidewall (see Fig. 17, column 4 and lines 17-20); a second doped region (right portion of region 82) disposed in the substrate and close to the second inner wall, the second doped region having different conductivity than the first conductivity type (p type different from n type) (see column 4 and lines 37-38); a first epitaxial region (only horizontal portion of layer 68) connected to the first inner sidewall of the substrate (electrically connected), the first epitaxial region comprising a first semiconductor material (not disclosed) having an impurity (n type doping) (see Fig. 17, column 4 and lines 2-10); and a second epitaxial region (layer 88) connected to the second inner sidewall of the substrate (electrically connected) and the first epitaxial region, the second epitaxial region comprising a second semiconductor material (germanium) (see Fig. 17, column 4 and lines 46-53).
Spencer fails to disclose the first epitaxial region comprising a first semiconductor material (silicon), so that the second semiconductor material has different band gap than the first semiconductor material.
Chen discloses a semiconductor structure comprising a first region (n-sub 318) comprising a first semiconductor material (silicon) with an impurity of a second conductivity type (n-type) (see Fig. 22 and [0059-0060]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the material of silicon of the first region of Chen (n-sub 318) into the semiconductor structure of Spencer for making the first semiconductor material of the second epitaxial region so that the second epitaxial region comprising the second semiconductor material (germanium) with different band gap than the first semiconductor material (silicon) because the modified structure would provide high performance photodetector with a silicon material for making n-type region and germanium for making p-type region for optimizing light absorption and fast carrier mobility and easier manufacturing with CMOS compatibility.
Regarding claim 14, the combination of Spencer and Chen discloses the semiconductor structure of claim 1, wherein the second epitaxial region overlies an uppermost surface of the first epitaxial region (layer 88 is over upper most surface of the horizontal portion of layer 38) (see Fig. 17 of Spencer).
Regarding claim 15, the combination of Spencer and Chen discloses the semiconductor structure of claim 1, wherein the first epitaxial region (the entire layer 68 being considered in claim 11 for rejecting claim 15) comprises a first portion (verticala portion of layer 68) connected to the first inner sidewall of the substrate (see Fig. 17 of Spencer) and a second portion (horizontal portion of layer 68) connected to the first portion, and a dimension of the first portion is greater than that of the second portion (the height of the vertical portion is greater than the height of the horizontal portion) (see Fig. 17 of Spencer).
Regarding claim 16, the combination of Spencer and Chen discloses the semiconductor structure of claim 11, wherein the first and second doped regions, the first and second epitaxial regions, and a portion of the substrate laterally between the first epitaxial region and the first doped region are included in an avalanche photodetector (photodetector device 60) (see Spencer, Fig. 17 and column 4, lines 28-65).
Regarding claim 17, Spencer discloses a manufacturing method of a semiconductor structure in Figs. 11-17, comprising: forming a first doped region (left portion of region 82) and a second doped region (right portion of region 74) in a substrate (substrate 62 same as substrate 12) (see column 4 and lines 17-20, lines 37-38), wherein the substrate comprising a first semiconductor material (silicon) (see column 2, lines 18-25 and column 4, line 1); the second doped region has a second conductivity type (n type) different than a first conductivity type of the first doped region (p type) (see column 4 and lines 37-38); forming a cavity (opening 66) in the substrate (see Fig. 11, column 4, lines 1-4); epitaxially growing a first epitaxial region (layer 68) in the cavity (opening 66), wherein the first epitaxial region comprising a first semiconductor material with an impurity of the second conductivity type (n type) (see column 4 and lines 2-10); and epitaxially grow a second epitaxial region (layer 88) in the cavity and on the first epitaxial region, the second epitaxial region comprising a second semiconductor material (germanium) (see column 4 and lines 46-53).
Spencer fails to disclose the method comprising the first epitaxial region comprising the first semiconductor material (silicon) so that the second semiconductor material different than the first semiconductor material.
Chen discloses a method of a semiconductor structure comprising forming a substrate (substrate 302) comprising a first semiconductor material (silicon) and forming a first region (n-sub 318) comprising the first semiconductor material (silicon) with an impurity of a second conductivity type (n-type) (see Fig. 22 and [0059-0060]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the material of silicon of the first region of Chen (n-sub 318) into the method of Spencer for making the first epitaxial region so that the second semiconductor material different than the first semiconductor material because the modified structure would provide high performance photodetector with a silicon material for making n-type region and germanium for making p-type region for optimizing light absorption and fast carrier mobility and easier manufacturing with CMOS compatibility.
Allowable Subject Matter
Claims 3, 8 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having:
Wherein the second epitaxial region comprises a curved upper surface protruded from the cavity of the substrate as recited in claim 3.
Wherein the capping layer comprises the first semiconductor material as recited in claim 8.
Wherein an upper surface of the second epitaxial region arcs between and is connected to the first and second inner sidewalls of the substrate as recited in claim 13.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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