DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 7/28/2026 have been fully considered but they are not persuasive. Applicant argues that layer 122 is between 124 and the conductive structure 120, and therefore layer 124 cannot be formed by oxidizing a surface region of the first conductive metal. However, elements 122 and 124 of Li are the same materials. Also, there is nothing in the claims that prevent the removal of the oxidation layer 116 of Uzoh. At least part of it must be removed for the interconnect structure to contact the first conductive metal. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Applicant also argues that reference Li does not disclose the hole to extend through the etch stop layer and the insulating film and stop at the conductive metal. However, the embodiment of Figure 8 shows the second interconnect (612) penetrating both the insulating film (124), layer 122, and the etch stop (114), and stopping at the first conductive metal (120).
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding the U.S.C. 112(b) rejection of claims 18-20, applicant’s arguments are persuasive; the limitation “the isolation layer” does in fact have sufficient antecedent basis, therefore the rejection is withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US Publication No. 2022/0359381) in view of Spooner et al. (US Publication No. 2017/0092590).
Regarding claim 1, Li discloses a method of manufacturing an integrated circuit device, comprising:
forming a semiconductor device (602) on a substrate (102)
forming a first interconnect structure (120) over the semiconductor device (602) and a dielectric layer to surround the first interconnect structure (120), wherein the first interconnect structure comprises a first conductive metal (120) electrically coupled to the semiconductor device through a plurality of first vias (116/118/106)
forming a second interconnect structure (612) over the first conductive metal (120), wherein the formation of the second interconnect structure comprises:
forming an insulating film (124) over the first conductive metal (120)
depositing an etch stop layer (114) over the insulating film (124), wherein the etch stop layer and the insulating film include different materials (paragraphs 35 and 65)
depositing an isolation layer (610) over the etch stop layer (114)
performing a first etching operation to form a hole penetrating through the isolation layer (610) to expose the etch stop layer (114)
causing the hole to extend through the etch stop layer (114) and the insulating film (124) and stop at the first conductive metal (120)
Li is silent regarding oxidizing a surface region of the first conductive metal, wherein the insulating film comprises an oxide of a material of the first conductive metal. However, Spooner discloses an insulating film (103) comprising an oxide of the first conductive metal (101) (paragraphs 16-17). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the first conductive metal to provide and oxide of said metal to clean and remove unwanted compounds, which improves both device reliability and performance (paragraph 17).
Regarding claim 2, Li discloses the insulating film (124) and the first conductive metal (120) have a substantially same pattern (Figure 2).
Regarding claim 3, Spooner discloses oxidizing the surface region of the first conductive metal comprises a plasma treatment including an O2 plasma operation (paragraph 17). As discussed above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Li in view of Spooner.
Regarding claim 4, Li discloses a lower surface and an upper surface of the insulating film (124) and an upper surface of the dielectric layer (112) are at different vertical levels (Figure 2).
Regarding claim 5, Li discloses the upper surface of the dielectric layer (112) is between the lower surface of the insulating film (124) and the upper surface of the insulating film (124) in a cross-sectional view (Figure 2B).
Regarding claim 6, Li discloses a lower surface of the insulating film (124 or 402) is flush with an upper surface of the dielectric layer (112 or 402) when viewed in a cross-sectional view.
Regarding claim 7, Li discloses depositing a conductive material (612) in the hole to form the second interconnect structure (612) connected to the first interconnect structure (120) (Figure 8).
Regarding claim 8, Li discloses the first interconnect structure has a thickness less than a thickness of the second interconnect structure (Figure 20).
Regarding claim 9, Li discloses performing a second etching operation to form a trench (614) in the isolation layer (610) and connected to the hole (612), wherein a width of the trench (614) is greater than a width of the hole (612); and depositing a conductive material (614) in the hole and the trench to form the second interconnect structure connected to the first interconnect structure (paragraphs 85-87).
Regarding claim 18, Li discloses an integrated circuit device, comprising:
a substrate (102) comprising a plurality of semiconductor devices (602)
an interconnect structure (120) electrically coupled to the substrate (102) and comprising:
a conductive metal (120) electrically coupled to the substrate
an insulating film (124) on the conductive metal (120), wherein the insulating film (124) and the conductive metal (120) comprise a common element
an etch stop layer (114) over the insulating film (124)
an isolation layer (610) over the etch stop layer (114)
a conductive via (614) penetrating the isolation layer (610), the etch stop layer (114) and the insulating film (124) and electrically coupled to the conductive metal (120)
Li is silent regarding oxidizing a surface region of the first conductive metal, wherein the insulating film comprises an oxide of a material of the first conductive metal. However, Spooner discloses an insulating film (103) comprising an oxide of the first conductive metal (101) (paragraphs 16-17). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the first conductive metal to provide and oxide of said metal to clean and remove unwanted compounds, which improves both device reliability and performance (paragraph 17).
Regarding claim 19, Li discloses the insulating film (124) and the conductive metal (120) have a substantially same pattern (614).
Regarding claim 20, Li discloses the conductive metal (120) has a thickness less than a thickness of the conductive via (614).
Claims 11, 14, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US Publication No. 2022/0359381) in view of Dogiamis et al. (US Publication No. 2022/0399294).
Regarding claim 11, Li discloses a method of manufacturing an integrated circuit device, comprising:
providing a first die (102), the first die comprising:
a first substrate (102)
a first interconnect structure (120) over the first substrate (102)
a first dielectric layer (112) to surround the first interconnect structure (120)
providing a second die, the second die comprising (paragraph 90):
a second substrate (104 upper)
a second interconnect structure (612) over the second substrate
a second dielectric layer (1806) to surround the second interconnect structure
an insulating film (124) on the second interconnect structure
an etch stop layer (114) over the second dielectric layer and the insulating film
an isolation layer (610) over the etch stop layer (114)
forming a hole (614) penetrating through the isolation layer (610) to expose the etch stop layer (114)
causing the hole (614) to extend through the etch stop layer (114) and the insulating film (124)
depositing a conductive material (612) in the hole to form a conductive via electrically coupled to the second interconnect structure (612)
Li does not specifically disclose the first and second dies to be separately fabricated. However, Dogiamis discloses bonding first (114-1) and second (114-2) separately fabricated dies by an interconnect structure (104). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the method of Li to include connecting two separately fabricated dies, as taught by Dogiamis, since it can improve device density through hybrid bonding of multiple dies at improved pitch with reduced surface area (paragraph 1).
Regarding claim 14, Li discloses a lower surface of the insulating film (124 or 402) is flush with an upper surface of the second dielectric layer (112 or 402) when viewed in a cross-sectional view.
Regarding claim 16, Li discloses bonding the first die to the second die, wherein the second die further includes a conductive pillar electrically coupled to the second interconnect structure and disposed under the insulating film, and the conductive pillar is physically connected to a topmost first interconnect structure after the first die and the second die are bonded (paragraphs 89-90).
Regarding claim 17, Li discloses bonding the first die to the second die, wherein after the first die and the second die are bonded, the second substrate is in contact with the first dielectric layer and portions of the first interconnect structure (paragraphs 89-90).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US Publication No. 2022/0359381) by in view of Dogiamis et al. (US Publication No. 2022/0399294), and further in view of Uzoh et al. (US Publication No. 2012/0319282).
Regarding claim 12, Li discloses the limitations as discussed in the rejection of claim 11 above. Li is silent regarding the formation of the insulating film comprises oxidizing the first conductive metal. However, Uzoh discloses forming insulation materials (206/214) around a first conductive metal (112) oxidizing a first conductive metal (112) (paragraph 17). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Li to include oxidizing the conductive metal to improve uniformity and reduce roughing of the metal, thereby improving the connection of the interconnect (paragraph 37).
Regarding claim 13, Li discloses a lower surface and an upper surface of the insulating film (124) and an upper surface of the second dielectric layer (1806) are at different vertical levels.
Claims 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US Publication No. 2022/0359381) by in view of Dogiamis et al. (US Publication No. 2022/0399294), and further in view of Chen et al. (US Publication No. 2023/0105036).
Regarding claim 10, Li discloses the limitations as discussed in the rejection of claim 9 above. Li does not disclose wherein the trench has a first depth greater than a thickness of the first interconnect structure. However, Chen discloses an upper interconnect with a trench thickness much larger (Sv) than the lower interconnect structure (Figure 3). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the trench depth of Li to be greater than the thickness of the lower interconnect structure, as taught by Chen, since it can increase voltage tolerance and prevent warpage on the substrate (paragraph (44).
Regarding claim 15, Li discloses the limitations as discussed in the rejection of claim 11 above. Li does not disclose wherein the hole has a depth greater than a thickness of the second interconnect structure. However, Chen discloses an upper interconnect with a trench thickness much larger (Sv) than the lower interconnect structure (Figure 3). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the hole depth of Li to be greater than the thickness of the lower interconnect structure, as taught by Chen, since it can increase voltage tolerance and prevent warpage on the substrate (paragraph (44).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
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/N.R.P/ 9/24/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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