Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the filing of the Applicant Arguments/Remarks Made in an Amendment on 06/04/2026. Currently, claims 1-20 are pending in the application. Claims 15-17 have been withdrawn from consideration.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 18-19 are rejected under 35 U.S.C. 103 as being obvious over CHEN (US 20220149195 A1) in view of Kawashima et al (US 20020185674 A1).
Regarding claim 1, Figure 9 of CHEN discloses a semiconductor device, comprising:
a substrate (101+107, [0067]);
a tunnel insulating layer (207, [0073]) disposed over the substrate (101);
a floating gate (211, [0073] and [0121]) disposed over the tunnel insulating layer (207);
a laterally oxidized intervention layer (209, [0073]) disposed over the floating gate (211), wherein the laterally oxidized intervention layer comprises a sidewall portion (209F, portions with dots) and a center portion (region in 209 without the dots), and the sidewall portion has an oxygen concentration greater than that of the center portion ([0092]);
first and second doped regions (301/303) spacedly formed in the substrate; and
a control gate (501, [0071]) disposed over the laterally oxidized intervention layer (209).
CHEN does not explicitly teach wherein the tunnel insulating layer (207) is formed between the first and second doped regions (301/303) at a position that two side walls of the tunnel insulating layer are aligned with side surfaces of the first and second doped regions.
However, Kawashima is a pertinent art which teaches a nonvolatile semiconductor storage device having formed a floating gate electrode on a tunneling insulation film. Figure 14 teaches such a memory cell in a nonvolatile semiconductor storage device wherein the doped regions (82) are formed in the substrate having two side walls of a tunnel insulating layer (83, [0077]) are aligned with side surfaces of the doped regions (82) in a method of forming a memory device wherein reliable writing is ensured without accurate control of the writing voltage, and it contributes to simplifying the configuration of the verify circuit and to realization of substantially high-speed writing ([0082]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of CHEN wherein the tunnel insulating layer (207) is formed between the first and second doped regions (301/303/305) at a position that two side walls of the tunnel insulating layer are aligned with side surfaces of the first and second doped regions according to the teaching of Kawashima in order to have a memory device wherein reliable writing is ensured without accurate control of the writing voltage, and it contributes to simplifying the configuration of the verify circuit and to realization of substantially high-speed writing ([0082], Kawashima).
Regarding claim 2, Figure 9 of CHEN discloses that the semiconductor device of claim 1, wherein the first and second doped regions (301/303) are disposed in the substrate (107) and are extended from a top surface of the substrate.
Regarding claim 3, Figure 9 of CHEN discloses that the semiconductor device of claim 2, further comprising a first well region (107, [0067]) in the substrate (107+107), wherein the first and second doped regions (301/303) are disposed in the first well region (107).
Regarding claim 4, Figure 9 of CHEN discloses that the semiconductor device of claim 3, further comprising a plurality of memory unit spacers (213, [0073]) disposed on the substrate and attached to the sidewalls of the tunnel insulating layer (207).
Regarding claim 5, Figure 9 of CHEN discloses that the semiconductor device of claim 4, further comprising a memory top conductive layer (217, [0099]) disposed over the control gate.
Regarding claim 6, Figure 9 of CHEN discloses that the semiconductor device of claim 5, wherein the laterally oxidized intervention layer (209) has a thickness between 10 angstroms and about 350 angstroms ([0077]).
Regarding claim 7, Figure 9 of CHEN discloses that the semiconductor device of claim 6, wherein the tunnel insulating layer (207) has a thickness different from a thickness of the laterally oxidized intervention layer (209), and the tunnel insulating layer is formed of a material different from the material of the laterally oxidized intervention layer ([0076]-[0077]).
Regarding claim 8, Figure 9 of CHEN discloses that the semiconductor device of claim 7, further comprising a passivation insulating layer (105, [0067]) disposed on the substrate (101), wherein the passivation insulating layer (105) covers the memory top conductive layer and the memory unit spacers (213).
Regarding claim 18, Figure 9 of CHEN discloses a semiconductor device, comprising:
a substrate (101, [0067]);
a tunnel insulating layer (207, [0076]) disposed over the substrate (101);
a floating gate (211, [0074] and [0121]) disposed over the tunnel insulating layer;
a laterally oxidized intervention layer (209, [0077]) disposed over the floating gate;
a control gate (501, [0067]) disposed over the laterally oxidized intervention layer; and
a selection unit (401, [0067]) disposed on the substrate (101), wherein the selection unit comprises a selection unit insulating layer (403, [0081]) and a selection unit conductive layer (405, [0081]).
CHEN does not explicitly teach a dope region disposed in the substrate and between a sidewall of the tunnel insulating layer (207) and a sidewall of the selection unit (401).
However, Kawashima is a pertinent art which teaches a nonvolatile semiconductor storage device having formed a floating gate electrode on a tunneling insulation film. Figure 14 teaches such a memory cell in a nonvolatile semiconductor storage device wherein the doped regions (82) are formed in the substrate having two side walls of a tunnel insulating layer (83, [0077]) are aligned with side surfaces of the doped regions (82) in a method of forming a memory device wherein reliable writing is ensured without accurate control of the writing voltage, and it contributes to simplifying the configuration of the verify circuit and to realization of substantially high-speed writing ([0082]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of CHEN wherein a dope region (303) disposed in the substrate (101) and between a sidewall of the tunnel insulating layer (207) and a sidewall of the selection unit (401) according to the teaching of Kawashima in order to have a memory device wherein reliable writing is ensured without accurate control of the writing voltage, and it contributes to simplifying the configuration of the verify circuit and to realization of substantially high-speed writing ([0082], Kawashima).
Regarding claim 19, Figure 9 of CHEN discloses that the semiconductor device of claim 18, wherein the selection unit (401) is separated from the floating gate (211).
Claims 9-11 and 20 are rejected under 35 U.S.C. 103 as being obvious over CHEN (US 20220149195 A1) in view of Kawashima et al (US 20020185674 A1) as applied to claims above, and further in view of Cheng et al (US 20170373162 A1).
Regarding claims 9-11, Figure 9 of CHEN discloses that the semiconductor device of claim 8, further comprising a plurality of doped region contacts (603, [0067], not shown in Figure 9 but shown in Figure 2) extending from a top surface of the passivation insulating layer (105) into the first and second doped regions (301/303) through the top surface of the substrate, wherein the doped region contacts (603) are electrically coupled to the first and second doped regions.
CHEN does not teach that the doped region contacts (603) are extending into the first and second doped regions (301/303), wherein the doped region contact comprises a lower portion and an upper portion, wherein the lower portion of the doped region contact extends into the doped region, and the upper portion of the doped region contact is surrounded by the passivation insulating layer; and wherein the lower portion of the doped region contact has a first critical dimension, and the upper portion of the doped region contact has a second critical dimension greater than the first critical dimension.
However, Cheng is a pertinent art which teaches a field effect transistor structure with reduced contact resistance, and more particularly to reduce contact resistance between source/drains doped region and conductive source drain contacts ([0001]), wherein Figure 16 of Cheng teaches such a source/drains contact (230, [0095]), wherein the source/drains contact is electrically coupled to doped regions (120), wherein the source/drains contact (doped region contact) comprises a lower portion (within 120) and an upper portion (above the layer 120), wherein the lower portion of the source/drains contact extends into the doped region (120), and the upper portion of the source/drains contact is surrounded by a passivation insulating layer (210); and wherein the lower portion of the source/drains contact (230) has a first critical dimension, and the upper portion of the doped region contact has a second critical dimension greater than the first critical dimension.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of CHEN as claimed according to the teaching of Cheng in order to improve contact resistance ([0001] of Cheng) between the doped region contacts (603) and the doped regions (301/303) in the device of CHEN.
Regarding claim 20, Figure 9 of CHEN discloses that the semiconductor device of claim 19, further comprising a doped region contact (63, please see Figure 2 for the contact) formed between the tunnel insulating layer (207) and the selection unit (401).
CHEN does not teach wherein the doped region contact has an upper portion extended above a top surface of the substrate and a lower portion extended into the doped region through the top surface of the substrate to electrically couple to the doped region.
However, Cheng is a pertinent art which teaches a field effect transistor structure with reduced contact resistance, and more particularly to reduce contact resistance between source/drains doped region and conductive source drain contacts ([0001]), wherein Figure 16 of Cheng teaches such a source/drains contact (230, [0095]), wherein the source/drains contact is electrically coupled to doped regions (120), wherein the source/drains contact (doped region contact) comprises a lower portion (within 120) and an upper portion (above the layer 120), wherein the lower portion of the source/drains contact extends into the doped region (120), and the upper portion of the source/drains contact is surrounded by a passivation insulating layer (210); and wherein the lower portion of the source/drains contact (230) has a first critical dimension, and the upper portion of the doped region contact has a second critical dimension greater than the first critical dimension.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of CHEN as claimed according to the teaching of Cheng in order to improve contact resistance ([0001] of Cheng) between the doped region contacts (603) and the doped regions (301/303) in the device of CHEN.
Claims 12-14 are rejected under 35 U.S.C. 103 as being obvious over CHEN (US 20220149195 A1) in view of Kawashima et al (US 20020185674 A1) and Cheng et al (US 20170373162 A1) as applied to claim 11 above, and further in view of Chen (US 6150267 A).
Regarding claims 12-14, Figure 9 of CHEN in view of Kawashima and Cheng do not teach that the semiconductor device of claim 11, wherein the first critical dimension gradually decreases at positions of increasing distance from a top surface of the substrate, while the second critical dimension is constant, wherein a peripheral surface of the lower portion of the doped region contact is discontinuous with a peripheral surface of the upper portion of the doped region contact; and wherein the lower portion of the doped region contact and the upper portion of the doped region contact are integrally formed.
However, Chen is a pertinent art which teaches a source/drain regions which gradually decreases at positions of increasing distance from a top surface of the substrate in Figure 3D in order to reduce contact resistance as well as leakage current (Col. 2, lines 50-55).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of CHEN in view of Cheng according to the teaching of Chen as claimed above in order to lower the leakage current (Col. 2, lines 50-55, Chen).
Response to Arguments
Applicant’s arguments/amendments regarding the rejection of claims 1-14 and 18-20, filed on 06/04/2026, have been fully considered but arguments are moot because newly added limitation to the claim (s) requires a new ground of rejection necessitated by amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday to Friday from 8:00 AM to 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/
Primary Examiner, Art Unit 2813
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