DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the application filed on 1/11/24.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 1/11/24 and 3/05/25. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 15 is objected to because of the following informalities: it appears that “component 20” needs to be corrected to read as “component”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 9, 11-15, and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US PGPub 2021/0057332, hereinafter referred to as “Chen”).
Chen discloses the semiconductor device as claimed. See figures 3A-5C and corresponding text where Chen teaches, in claim 1, a device, comprising:
a first dielectric layer (140) disposed over a carrier (TC) (located in (10B1), figures 4B and 4C; [0048]);
a second dielectric layer (120) disposed over and having a bonded interface with the first dielectric layer (140), the second dielectric layer (120) comprising silicon oxide, the second dielectric layer (120) (includes a low-k dielectric or extreme low-K (ELK) material [0028]) comprising a different composition than the first dielectric layer (140) (contains a high-density plasma (HDP) oxide [0032]); (figures 4A and 4C; [0028-0032]) (located in (10B1))
a third dielectric layer (120) (interlayer dielectric material (ILD [0028]) disposed over and physically contacting the second dielectric layer, the third dielectric layer comprising silicate glass (located in (10B2) where (140) is an undoped silicate glass (USG) [0032]);
a first interconnect structure (130) disposed over the third dielectric layer (120); and (located in (10B1))
a conductive connector (150) disposed over the first interconnect structure (130). (located in (10B2)) (figure 4C; [0049])
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Chen teaches, in claim 2, further comprising:
a device layer (10B1) disposed over the first interconnect structure; and a second interconnect structure (10B2) disposed over the device layer (figure 4C; [0029], [0059]).
Chen teaches, in claim 3, wherein the third dielectric layer (120) comprises a lesser density (includes a low-k dielectric or extreme low-K (ELK) material [0028]) than that of the second dielectric layer (140) (contains a high-density plasma (HDP) oxide [0032]).
Chen teaches, in claim 4, further comprising a substrate interposed between the first interconnect structure and the conductive connector, the substrate comprising a semiconductor material (figures 4B- 5C; [0048-0050]).
Chen teaches, in claim 5, further comprising a conductive via extending through the substrate, the conductive via electrically connecting the first interconnect structure to the conductive connector (figures 4B- 5C; [0048-0050]).
Chen teaches, in claim 6, wherein the third dielectric layer has a thickness of greater than 600 nm ([0051]).
Chen teaches, in claim 7, further comprising a semiconductor substrate interposed between the first interconnect structure and the conductive connector (figures 4B- 5C; [0048-0050]).
Chen teaches, in claim 8, further comprising a conductive via extending through the semiconductor substrate and electrically connected to the conductive connector (figures 4B- 5C; [0048-0050]).
Chen teaches, in claim 9, a device, comprising:
a device layer (10C) disposed over a substrate (TC);
a first interconnect structure (130) disposed over the device layer (10C) (located in (10B1);
a first oxide layer (140) disposed over the first interconnect structure (130);
a second oxide layer (120) disposed over the first oxide layer (140), the second oxide layer (120) comprising a different composition than the first oxide layer comprising a different composition (includes a low-k dielectric or extreme low-K (ELK) material [0028]) than the first dielectric layer (140) (contains a high-density plasma (HDP) oxide [0032]); (figures 4A and 4C; [0028-0032]) (located in (10B1));
a conductive feature (130) extending from the first interconnect structure (130) to an upper surface of the second oxide layer (120), (located in (10C)) the upper surface of the second oxide layer (120) facing away from the first interconnect structure (130); and
an integrated circuit die (10B2) disposed over the second oxide layer (120), a die connector (150) of the integrated circuit die (10B2) being bonded to the conductive feature (130) (located in (10B2)) (figure 4C; [0049]).
Chen teaches, in claim 11, wherein a dielectric layer of the integrated circuit die is bonded to the second oxide layer (located in (10B2) where (140) is an undoped silicate glass (USG) [0032]).
Chen teaches, in claim 12, wherein a metal-to-metal bond directly bonds the die connector to the conductive feature, and wherein a dielectric-to-dielectric bond directly bonds the dielectric layer to the second oxide layer ([0046], [0055]).
Chen teaches, in claim 13, wherein a thickness of the first oxide layer is greater than about 600 nm ([0051]).
Chen teaches, in claim 14, wherein a thickness of the second oxide layer is between about 800 nm and about 2400 nm ([0051]).
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Chen teaches, in claim 15, a device, comprising:
a first semiconductor component (10C) comprising a first substrate;
a second semiconductor component (10B1) over the first semiconductor component (10C), the second semiconductor component comprising an interconnect structure (130); and
a bonding region interposed between the first semiconductor component (10C) and the second semiconductor component (10B1), the bonding region comprising:
a first bonding layer (120) disposed along the first substrate of the first semiconductor component (10C) (figures 4A and 4C; [0045-0047]);
a buffer layer (140) disposed along the interconnect structure (130) of the second semiconductor component (10B1), the buffer layer comprising an undoped silicate glass (figure 4C; [0051-0052]); and
a second bonding layer (120) directly interposed between the first bonding layer and the buffer layer (140), the second bonding layer comprising a high density plasma oxide (figure 4C; [0051-0052], location in (10B1) the examiner views that the second bonding layer is a multi-layered structure).
Chen teaches, in claim 17, wherein the density of the second bonding layer (120) is greater than the density of the buffer layer (140) (includes a low-k dielectric or extreme low-K (ELK) material [0028]) and (140) (contains a high-density plasma (HDP) oxide [0032]); (figures 4A and 4C; [0028-0032]).
Chen teaches, in claim 18, wherein the bonding region further comprises:
a die connector embedded in the first bonding layer; and
a conductive feature (150) embedded in the second bonding layer (figures 4C and 5A; [0051-0054]).
Chen teaches, in claim 19, wherein the die connector is direct bonded to the conductive feature (150).
Chen teaches, in claim 20, wherein the conductive feature extends from the die connector to the interconnect structure (130) (figures 4C and 5A; [0051-0054]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US PGPub 2021/0057332, hereinafter referred to as “Chen”) as applied to claims 1 and 15 above, and further in view of Xiao et al. (US PGPub 2020/0075323, hereinafter referred to as “Xiao”).
Chen disclose the semiconductor device substantially as claimed. See the rejection above.
However, Chen fails to show, in claim 10, wherein the first oxide layer comprises a first high density plasma oxide, wherein the second oxide layer comprises a second high density plasma oxide, and wherein the second oxide layer has a higher density than the first oxide layer.
Xiao teaches, in claim 10, a composition of low-K dielectrics formed that include a high density plasma process ([0057]), where the density of the films is less than 2.0 g/mL, less than 1.5 g/mL, or less than 1.25 g/mL ([0068]). In addition, Xiao provides the advantages of having insulating materials with “K” values drop below 2.7 where various porous materials for improved insulating properties contain a desirable balance of electrical and mechanical properties, thermal stability, and chemical resistance using conventional techniques to control the carbon content within the film. ([0003], [0016],[0065]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate wherein the first oxide layer comprises a first high density plasma oxide, wherein the second oxide layer comprises a second high density plasma oxide, and wherein the second oxide layer has a higher density than the first oxide layer, in the device of Chen, according to the teachings of Xiao, with the motivation of improved insulating properties contain a desirable balance of electrical and mechanical properties, thermal stability, and chemical resistance using conventional techniques to control the amount of carbon.
Chen fails to show, in claim 16, wherein a density of the buffer layer is between about 2.0 g/mL and about 2.5 g/mL, and wherein a density of the second bonding layer is between about 2.0 g/mL and 2.5 g/mL.
Xiao teaches, in claim 10, a composition of low-K dielectrics formed that include a high density plasma process ([0057]), where the density of the films is less than 2.0 g/mL, less than 1.5 g/mL, or less than 1.25 g/mL ([0068]). In addition, Xiao provides the advantages of having insulating materials with “K” values drop below 2.7 where various porous materials for improved insulating properties contain a desirable balance of electrical and mechanical properties, thermal stability, and chemical resistance using conventional techniques to control the carbon content within the film. ([0003], [0016],[0065]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate wherein a density of the buffer layer is between about 2.0 g/mL and about 2.5 g/mL, and wherein a density of the second bonding layer is between about 2.0 g/mL and 2.5 g/mL, in the device of Chen, according to the teachings of Xiao, with the motivation of improved insulating properties contain a desirable balance of electrical and mechanical properties, thermal stability, and chemical resistance using conventional techniques to control the amount of carbon.
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 December 13, 2025