CTNF 18/410,195 CTNF 101954 DETAILED ACTION This Office Action is in response to Application filed on January 11, 2024. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicants’ election without traverse of Group II and Species B drawn to an integrated circuit structure as recited in claim 1 and drawn to the embodiments shown in Figs. 4A and 4B, claims 1-9, 18-19 and newly added claims 21-29, in the reply filed on May 19, 2026 is acknowledged. Claims 3, 18-19, and 23 are withdrawn from examination, because the claimed dielectric material layer embedded in the epitaxial semiconductor feature recited in claims 3, 18-19 and 23, which is shown in Fig. 3D of current application, is not directed to the elected species, while the claimed dielectric material layer disposed on the bottom surface of the epitaxial semiconductor feature recited in claim 4 is directed to the elected species. Claim Objections 07-29-01 AIA Claim s 24 and 25 are objected to because of the following informalities: On line 2 of claim 24, the term “backside via” should be written as “backside conductive via”. On line 1 of claim 25, the term “backside via” should be written as “backside conductive via” . Appropriate correction is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 4, it is not clear how the dielectric material layer can be included in the claimed source or drain, because the dielectric material layer should be an insulating layer rather than an electrically conducting or semiconducting layer, and therefore, electrical charges would not move freely inside the claimed dielectric material layer for the claimed dielectric material layer to function as a part of a source or drain. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang et al. (US 20210202385 A1) hereinafter referred to as “Huang” . Regarding claim 1, Huang discloses an integrated circuit (IC) structure (Fig. 19), comprising: a semiconductor substrate (element 102B) ([0022]) having a frontside and a backside, because Merriam-Webster dictionary defines “substrate” as “an underlying support”, and the silicon layer 102B would function or act as an underlying support for a device structure formed on it; a shallow trench isolation (STI) structure (element 104) ([0023]) formed in the semiconductor substrate (element 102B) and defining an active region (element 106) ([0013]), wherein the STI structure (element 104) includes a STI bottom surface, wherein the semiconductor substrate (element 102B) includes a substrate bottom surface, and wherein the STI bottom surface and the substrate bottom surface are coplanar; a field-effect transistor (FET) (element 300, paragraph [0020]) over the active region (element 106) and formed on the frontside of the semiconductor substrate (element 102B); and a backside dielectric layer (element 122) ([0017]) disposed on the substrate bottom surface and the STI bottom surface . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 2, and 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 21-22, and 24-29 are allowed because Huang et al. do not disclose the limitation "a backside conductive via ... isolated from the semiconductor substrate by a dielectric barrier layer" recited in claim 21. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANGELICA ROSE E. GALVAN whose telephone number is (571)270-0122. The examiner can normally be reached Monday - Friday 8:30am - 6:00pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C KIM/Primary Examiner, Art Unit 2815 /ANGELICA ROSE GALVAN/Examiner, Art Unit 2815 Application/Control Number: 18/410,195 Page 2 Art Unit: 2815
Prosecution Insights