Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to Election/Restriction, applicant elected claims 1-17. Election was made without traverse in the reply filed on 04/28/2026.
Double Patenting
The provisional nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A provisional nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-17 and 21-23 are rejected on the ground of provisional nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. patent application No. 19261,999 (Hereinafter ‘999). Although the claims at issue are not identical, they are not patentably distinct from each other because:
With respect to claim 1: ‘999 discloses:
A method of forming a semiconductor package, the method comprising (Claim 1):
surrounding a die with a molding material (Claim 1); and
forming a redistribution structure (RDS) over the molding material and electrically coupled to the die (Claim 1), comprising:
depositing a first dielectric layer over the molding material; patterning the first dielectric layer to form a first plurality of openings in the first dielectric layer (Claim 1);
performing a first descum process to clean the first plurality of openings; after performing the first descum process, forming a first redistribution layer (RDL) on the first dielectric layer (Claim 1);
depositing a second dielectric layer over the molding material; patterning the second dielectric layer to form a second plurality of openings in the second dielectric layer (Claim 1);
performing a second descum process to clean the second plurality of openings, wherein the first descum process and the second descum process are performed under different process conditions (Claim 1); and
after performing the second descum process, forming a second RDL on the second dielectric layer (Claim 1).
With respect to claim 13: ‘999 discloses:
A method of forming a semiconductor package, the method comprising (Claim 13):
forming a molding material around a die (Claim 13);
forming a first dielectric layer over the molding material using a polymer material (Claim 13);
patterning the first dielectric layer to form a first plurality of openings in the first dielectric layer (Claim 13);
after patterning the first dielectric layer, performing a first descum process, wherein the first descum process is a first plasma process performed at a first pressure for a first duration of time (Claim 13);
after performing the first descum process, forming an electrically conductive material in the first plurality of openings and over an upper surface of the first dielectric layer to form a first redistribution layer (RDL) (Claim 13);
forming a second dielectric layer over the first dielectric layer using the polymer material (Claim 13);
patterning the second dielectric layer to form a second plurality of openings in the second dielectric layer (Claim 13);
after patterning the second dielectric layer, performing a second descum process, wherein the second descum process is a second plasma process performed at a second pressure for a second duration of time, wherein the second pressure is different from the first pressure, and the second duration of time is different from the first duration of time (Claim 13); and
after performing the second descum process, forming the electrically conductive material in the second plurality of openings and over an upper surface of the second dielectric layer to form a second RDL (Claim 13).
With respect to claim 21: ‘999 discloses:
A method of forming a semiconductor package, the method comprising (Claim 13):
embedding a die in a molding material (Claim 13); and
forming a redistribution structure (RDS) over the molding material and the die,
comprising (Claim 13):
forming a first dielectric layer over the molding material (Claim 13);
forming a first plurality of openings in the first dielectric layer (Claim 13);
performing a first descum process to clean the first plurality of openings,
wherein performing the first descum process results in a first surface roughness for an upper surface of the first dielectric layer distal from the molding material (Claim 13);
after performing the first descum process, forming an electrically conductive material in the first plurality of openings and along the upper surface of the first dielectric layer (Claim 13);
forming a second dielectric layer over the first dielectric layer (Claim 13);
forming a second plurality of openings in the second dielectric layer (Claim 13);
performing a second descum process to clean the second plurality of
openings, wherein the first descum process and the second descum process are
performed under different process conditions, wherein performing the second descum process results in a second surface roughness for an upper surface of the second dielectric layer distal from the molding material, wherein the second surface roughness is higher than the first surface roughness (Claim 16); and
after performing the second descum process, forming the electrically
conductive material in the second plurality of openings and along the upper surface of
the second dielectric layer (Claim 13).
Claims 2-12, 14-17 and 22-23 are rejected on the ground of provisional nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. patent application No. 19261,999 (Hereinafter ‘999).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2017/0110421, hereinafter Liu) in view of Kuo et al. (US 2021/0090995, hereinafter Kuo).
With respect to claim 1, Liu discloses a method of forming a semiconductor package (Fig. 5A), the method comprising: surrounding a die (201/301) with a molding material (401); and forming a redistribution structure (RDS) (500 ) over the molding material and electrically coupled to the die (500 is over 401 and is electrically coupled to 201/301), comprising: depositing a first dielectric layer (501 of Fig. 5B) over the molding material; patterning the first dielectric layer to form a first plurality of openings in
the first dielectric layer (there are multiple openings in 501);
performing a first descum process to clean the first plurality of openings (para 0050 – descum treatment); after performing the first descum process, forming a first redistribution layer (RDL) (509) on the first dielectric layer; depositing a second dielectric layer (511) over the molding material; patterning the second dielectric layer to form a second plurality of openings in the second dielectric layer (there are multiple openings in layer 511).
Liu does not explicitly disclose performing a second descum process to clean the second plurality of openings, wherein the first descum process and the second descum process are performed under different process conditions; and after performing the second descum process, forming a second RDL on the second dielectric layer.
In an analogous art, Kuo discloses performing a second descum process to clean the second plurality of openings (Para 0030 – second cleaning step), wherein the first descum process and the second descum process are performed under different process conditions (Para 0029, 0031; SN1 is in a range of pH 0.5 to pH 5 & SN2 in a range of pH 1.5 to pH 6); and after performing the second descum process, forming a second RDL on the second dielectric layer (para 0037).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu’s method by having Kuo’s disclosure in order to prevent over etching or damages to the surfaces of the semiconductor device.
With respect to claim 21, Liu discloses a method of forming a semiconductor package (Fig. 5A), the method comprising: embedding a die (201/301) in a molding material (401); and forming a redistribution structure (RDS) (500) over the molding material and the die (Fig. 5A), comprising: forming a first dielectric layer (501 of Fig. 5B) over the molding material; forming a first plurality of openings in the first dielectric layer (there are opening in 501); performing a first descum process to clean the first plurality of openings (para 0050 – descum treatment; after performing the first descum process, forming an electrically conductive material (509) in the first plurality of openings and along the upper surface of the first dielectric layer (Fig. 5B); forming a second dielectric layer (511) over the first dielectric layer (Fig. 5B); forming a second plurality of openings in the second dielectric layer (openings in 511).
Liu does not explicitly disclose wherein performing the first descum process results in a first surface roughness for an upper surface of the first dielectric layer distal from the molding material; performing a second descum process to clean the second plurality of openings, wherein the first descum process and the second descum process are performed under different process conditions, wherein performing the second descum process results in a second surface roughness for an upper surface of the second dielectric layer distal from the molding material, wherein the second surface roughness is higher than the first surface roughness; and after performing the second descum process, forming the electrically conductive material in the second plurality of openings and along the upper surface of the second dielectric layer.
In an analogous art, Kuo discloses wherein performing the first descum process results in a first surface roughness for an upper surface of the first dielectric layer distal from the molding material (Para 0028); performing a second descum process to clean the second plurality of openings (Para 0030 – second cleaning step), wherein the first descum process and the second descum process are performed under different process conditions (Para 0029, 0031; SN1 is in a range of pH 0.5 to pH 5 & SN2 in a range of pH 1.5 to pH 6), wherein performing the second descum process results in a second surface roughness for an upper surface of the second dielectric layer distal from the molding material (Para 0030), wherein the second surface roughness is higher than the first surface roughness (Abstract and Para 0036); and after performing the second descum process, forming the electrically conductive material in the second plurality of openings and along the upper surface of the second dielectric layer (para 0037).Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu’s method by having Kuo’s disclosure in order to prevent over etching or damages to the surfaces of the semiconductor device.
Claims 2-8, 11-16 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Liu/Kuo in view of Lan (CN 112609168, hereinafter Lan).
With respect to claim 2, Liu/Kuo discloses the method of claim 1.
Liu/Kuo does not explicitly disclose wherein the first descum process is performed under a first process condition at a first pressure for a first duration of time, and the second descum process is performed under a second process condition at a second pressure for a second duration of time, wherein the first pressure is different from the second pressure, and the first duration of time is different from the second duration of time.
In an analogous art, Lan discloses wherein the first descum process is performed
under a first process condition at a first pressure for a first duration of time, and the
second descum process is performed under a second process condition at a second
pressure for a second duration of time, wherein the first pressure is different from the
second pressure, and the first duration of time is different from the second duration of
time (Page 04, para 02; Page 05, para 02; Page 07, last para– time and pressure are different for first and second cleaning process).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu/Kuo’s method by having Lan’s disclosure in order to achieve the optimal results for cleaning a semiconductor device.
With respect to claim 13, Liu discloses a method of forming a semiconductor package (Fig. 5A), the method comprising: forming a molding material (401) around a die (201/301); forming a first dielectric layer (501 of Fig. 5B) over the molding material using a polymer material (Para 0045 – polyimide); patterning the first dielectric layer to form a first plurality of openings in the first dielectric layer (Fig.5B – there are multiple openings in 501); after patterning the first dielectric layer, performing a first descum process (Para 0050 – descum process), wherein the first descum process is a first plasma process (Para 0050 -plasma treatment) performed at a first pressure (Para 0131) for a first duration of time (descum process time);
after performing the first descum process, forming an electrically conductive material (505) in the first plurality of openings and over an upper surface of the first dielectric layer to form a first redistribution layer (RDL) (Fig. 5B); forming a second dielectric layer (507) over the first dielectric layer using the polymer material (Para 0061 – polyimide); patterning the second dielectric layer to form a second plurality of openings in the second dielectric layer (there are openings in 507).
Liu does not explicitly disclose after patterning the second dielectric layer, performing a second descum process; and after performing the second descum process, forming the electrically conductive material in the second plurality of openings and over an upper surface of the second dielectric layer to form a second RDL.
In an analogous art, Kuo discloses after patterning the second dielectric layer, performing a second descum process (para 0030 – second cleaning process); and after performing the second descum process, forming the electrically conductive material in the second plurality of openings and over an upper surface of the second dielectric layer to form a second RDL (Para 0032, 0034; Fig. 1I & 1J).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu’s method by having Kuo’s disclosure in order to prevent over etching or damages to the surfaces of the semiconductor device.
Liu/Kuo does not explicitly disclose wherein the second descum process is a second plasma process peformed at a second pressure for a second duration of time, wherein the second pressure is different from the first pressure, and the second duration of time is different from the first duration of time.
In an analogous art, Lan discloses wherein the second descum process is a second plasma process (Page 02; Abstract – second plasma process for cleaning) performed at a second pressure for a second duration of time, wherein the second pressure is different from the first pressure, and the second duration of time is different from the first duration of time (Page 04, para 02; Page 05, para 02; Page 07, last para– time and pressure are different for first and second cleaning process).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu/Kuo’s method by having Lan’s disclosure in order to achieve the optimal results for cleaning a semiconductor device.
With respect to claims 3 and 14, Liu/Kuo/Lan discloses the method of claim 2.
Liu/Kuo does not explicitly disclose wherein the second pressure is lower than the first pressure, and the second duration of time is longer than the first duration of time.
In an analogous art, Lan discloses wherein the second pressure is lower than the
first pressure, and the second duration of time is longer than the first duration of time (Page 07; Para 02-03; Page 08; Para 01-02 – it’s obvious pressure and time can be adjusted for first and second cleaning steps).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu/Kuo’s method by having Lan’s disclosure in order to achieve the optimal results for cleaning a semiconductor device.
With respect to claims 4 and 15, Liu/Kuo/Lan discloses the method of claim 3.
Liu/Kuo does not explicitly disclose wherein the second pressure is
between about 30% and about 70% of the first pressure, and wherein the second
duration of time is between about one time and about five times the first duration
of time.
In an analogous art, Lan discloses wherein the second pressure is
between about 30% and about 70% of the first pressure (Page 08; last Para), and wherein the second duration of time is between about one time and about five times the first duration of time (Page 08; Para 02 and Page 09; First Para).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu/Kuo’s method by having Lan’s disclosure in order to achieve the optimal results for cleaning a semiconductor device.
With respect to claim 5, Liu discloses wherein the first dielectric layer and the second dielectric layer are formed of a same polymer material (Para 0021 and 0032 – polyimide).
With respect to claim 6, Liu/Kuo/Land discloses the method of clai3.
Liu does not explicitly disclose wherein the first descum process results in a first surface roughness parameter Rq for an upper surface of the first dielectric layer distal from the molding material, wherein the second descum process results in a second surface roughness parameter Rq for an upper surface of the second dielectric layer distal from the molding material, wherein the second surface roughness parameter Rq is larger than the first surface roughness parameter Rq.
In an analogous art, Kuo discloses wherein the first descum process results in a first surface roughness parameter Rq for an upper surface of the first dielectric layer distal from the molding material (Para 0028), wherein the second descum process results in a second surface roughness parameter Rq for an upper surface of the second dielectric layer distal from the molding material (Para 0030 – second cleaning step), wherein the second surface roughness parameter Rq is larger than the first surface roughness parameter Rq (Abstract and Para 0036).Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu’s method by having Kuo’s disclosure in order to prevent over etching or damages to the surfaces of the semiconductor device.
With respect to claim 7, Liu discloses wherein forming the first RDL comprises
forming an electrically conductive material in the first plurality of openings and on the
first dielectric layer (Fig. 5B – 505), wherein forming the second RDL comprises forming the electrically conductive material in the second plurality of openings and on the second dielectric layer (509/513).
With respect to claim 8, Liu disclose wherein the electrically conductive material
on the first dielectric layer is formed to have a first thickness (Para 0074), and the electrically conductive material on the second dielectric layer is formed to have a second thickness larger than the first thickness (Para 0076, Fig. 5B – 505/509/513 have different thickness).
With respect to claim 11, Liu disclose wherein the second dielectric layer is
deposited before the first dielectric layer such that the second dielectric layer is
between the molding material and the first dielectric layer (Fig. 5A-5B – there are multiple dielectric layers 501/507/511/515 on 401).
With respect to claim 12, Liu disclose wherein the second dielectric layer is
deposited after the first dielectric layer such that the first dielectric layer is between
the molding material and the second dielectric layer. (Fig. 5A-5B – there are multiple dielectric layers 501/507/511/515 on 401).
With respect to claim 16, Liu does not explicitly disclose wherein the first descum process results in a first surface roughness for the upper surface of the first dielectric layer, and the second descum process results in a second surface roughness for the upper surface of the second dielectric layer, wherein the second surface roughness is higher than the first surface roughness.
In an analogous art, Kuo discloses wherein the first descum process results in a first surface roughness for the upper surface of the first dielectric layer (Para 0030), and the second descum process results in a second surface roughness for the upper surface of the second dielectric layer (Para 0032), wherein the second surface roughness is higher than the first surface roughness (abstract and Para 0036).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu/Kuo’s method by having Lan’s disclosure in order to achieve the optimal results for cleaning a semiconductor device.
With respect to claim 22, Liu discloses that the first descum process is a first
plasma process performed at a first pressure for a first duration of time (Para 0050 -plasma treatment – time and pressure at the cleaning time).
Liu does not explicitly disclose that wherein the second descum process is a second plasma process performed at a second pressure for a second duration of time, wherein the second pressure is lower than the first pressure, and the second duration of time is longer than the first duration of time.
In an analogous art, Kuo discloses that wherein the second descum process is a second plasma process performed at a second pressure for a second duration of time, wherein the second pressure is lower than the first pressure, and the second duration of time is longer than the first duration of time.
(Page 07; Para 02-03; Page 08; Para 01-02 – it’s obvious pressure and time can be adjusted for first and second cleaning steps).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu/Kuo’s method by having Lan’s disclosure in order to achieve the optimal results for cleaning a semiconductor device.
Claims 9, 17 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Liu/Kuo/Lan in view of LV (CN 217085332, hereinafter LV).
With respect to claim 9, Liu disclose wherein forming the RDS further comprises after performing the first descum process and before forming the first RDL, conformally forming a first seed layer in the first plurality of openings and on the first dielectric layer, wherein forming the first RDL comprises forming the electrically conductive material on the first seed layer (Para 0019; 0022).
Liu does not explicitly disclose after performing the second descum process and before forming the second RDL, conformally forming a second seed layer in the second plurality of openings and on the second dielectric layer, wherein forming the second RDL comprises forming the electrically conductive material on the second seed layer, wherein the first seed layer and the second seed layer are formed of a same material.
In an analogous art, Kuo discloses after performing the second descum process and before forming the second RDL, conformally forming a second seed layer in the second plurality of openings and on the second dielectric layer, wherein forming the second RDL comprises forming the electrically conductive material on the second seed layer, wherein the first seed layer and the second seed layer are formed of a same material (Para 0034 – there are multiple layers of seed layers formed after first and second RDLs comprising of same material).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu’s method by having Kuo’s disclosure in order to prevent over etching or damages to the surfaces of the semiconductor device.
Liu/Kuo/Lan does not explicitly disclose wherein a second reflectivity
of the second seed layer is lower than a first reflectivity of the first seed layer.
In an analogous art, LV discloses wherein a second reflectivity
of the second seed layer is lower than a first reflectivity of the first seed layer. (Page 11; Para 02).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu/Kuo/Lan’s method by having LV’s disclosure in order to achieve the optimal results to perform the desired tasks.
With respect to claim 17, Liu disclose after performing the first descum process and before forming the electrically conductive material in the first plurality of openings, forming a first seed layer in the first plurality of openings and over the upper surface of the first dielectric layer, wherein the first seed layer has a first reflectivity (Para 0019; 0022).
Liu does not explicitly disclose after performing the second descum process and before forming the electrically conductive material in the second plurality of openings, forming a second seed layer in the second plurality of openings and over the upper surface of the second dielectric layer.
In an analogous art, Kuo discloses after performing the second descum process and before forming the electrically conductive material in the second plurality of openings, forming a second seed layer in the second plurality of openings and over the upper surface of the second dielectric layer (Para 0034 – there are multiple layers of seed layers formed after first and second RDLs comprising of same material).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu’s method by having Kuo’s disclosure in order to prevent over etching or damages to the surfaces of the semiconductor device.
Liu/Kuo/Lan does not explicitly disclose wherein the second seed layer has a second reflectivity different from the first reflectivity.
In an analogous art, LV discloses wherein the second seed layer has a second reflectivity different from the first reflectivity (Page 11; Para 02).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu/Kuo/Lan’s method by having LV’s disclosure in order to achieve the optimal results to perform the desired tasks.
With respect to claim 23, Liu disclose after performing the first descum process and before forming the electrically conductive material in the first plurality of openings, forming a first seed layer in the first plurality of openings and over the upper surface of the first dielectric layer, wherein the first seed layer has a first reflectivity (Para 0019; 0022).
Liu does not explicitly disclose after performing the second descum process and before forming the electrically conductive material in the second plurality of openings, forming a second seed layer in the second plurality of openings and over the upper surface of the second dielectric layer.
In an analogous art, Kuo discloses after performing the second descum process and before forming the electrically conductive material in the second plurality of openings, forming a second seed layer in the second plurality of openings and over the upper surface of the second dielectric layer (Para 0034 – there are multiple layers of seed layers formed after first and second RDLs comprising of same material).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu’s method by having Kuo’s disclosure in order to prevent over etching or damages to the surfaces of the semiconductor device.
Liu/Kuo/Lan does not explicitly disclose wherein the second seed layer has a second reflectivity lower than the first reflectivity.
In an analogous art, LV discloses wherein the second seed layer has a second reflectivity lower than the first reflectivity (Page 11; Para 02).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu/Kuo/Lan’s method by having LV’s disclosure in order to achieve the optimal results to perform the desired tasks.
Liu does not explicitly disclose after performing the second descum process and before forming the second RDL, conformally forming a second seed layer in the second plurality of openings and on the second dielectric layer, wherein forming the second RDL comprises forming the electrically conductive material on the second seed layer, wherein the first seed layer and the second seed layer are formed of a same material.
In an analogous art, Kuo discloses after performing the second descum process and before forming the second RDL, conformally forming a second seed layer in the second plurality of openings and on the second dielectric layer, wherein forming the second RDL comprises forming the electrically conductive material on the second seed layer, wherein the first seed layer and the second seed layer are formed of a same material (Para 0034 – there are multiple layers of seed layers formed after first and second RDLs comprising of same material).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu’s method by having Kuo’s disclosure in order to prevent over etching or damages to the surfaces of the semiconductor device.
Liu/Kuo/Lan does not explicitly disclose wherein a second reflectivity
of the second seed layer is lower than a first reflectivity of the first seed layer.
In an analogous art, LV discloses wherein a second reflectivity
of the second seed layer is lower than a first reflectivity of the first seed layer. (Page 11; Para 02).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liu/Kuo/Lan’s method by having LV’s disclosure in order to achieve the optimal results to perform the desired tasks.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 10, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the first reflectivity is about 45%, and the second reflectivity is about 15%.” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
Conclusion
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
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