DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicants’ amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US-20060019445-A1; Chen) in view of Yu et al. (US-20190214344-A1; Yu).
Regarding claim 10, Chen discloses a method for manufacturing a semiconductor structure, comprising: forming a gate structure (Fig. 1F, 104a/406a/408a; ¶30) on a substrate (Fig. 1F, 100; ¶28); forming gate spacers (Fig. 1F, 112; ¶29) at opposite sidewalls of the gate structure; forming a source portion (Fig. 1I, 115; ¶31) and a drain portion (Fig. 1I, 126; ¶35) in the substrate respectively at two opposite sides of the gate structure; forming a patterned protection layer (Fig. 1G, 116; ¶35) that covers the gate spacers, the source portion and the drain portion, and that exposes a top surface of the gate structure..; and performing a silicidation process (Fig. 1H,; ¶37) to form a silicide layer on the exposed gate structure.
At issue is the height dimension of the sidewall spacers and/or the height dimension of the gate structure.
Chen is silent on a top surface of the gate structure which is flush with a top surface of the gate spacers.
Yu discloses wherein a top surface of the gate structures is flush with the gate spacer. (Fig. 3, 750; ¶60)
This represents a change in size or proportion of disclosed elements which would not change the function of the elements. Therefore, before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to make a top surface coplanar or flush with the spacer layer for simplifying the deposition of subsequent layers. Also, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed elements are not patentably distinct from the prior art element. MPEP 2144.04 (IV)(A)
Regarding claim 11, Chen in view of Yu discloses the method according to claim 10, wherein in the silicidation process (Fig. 1H,; ¶37 Chen), the source portion (Fig. 1I, 115; ¶31 Chen) and the drain portion (Fig. 1I, 126; ¶35 Chen) are prevented from being silicided.
Regarding claim 12, Chen in view of Yu discloses the method according to claim 10, wherein the gate structure (Fig. 1F, 102a/104a/106a/108a; ¶30 Chen) includes a gate electrode and a gate dielectric disposed to separate the gate electrode from the substrate, the gate electrode being made of polysilicon.(¶26/28 Chen)
Regarding claim 13, Chen in view of Yu discloses the method according to claim 10, further comprising: but is silent on forming a source contact and a drain contact , each of which penetrates the protection layer and each of which is connected to a respective one of the source portion and the drain portion; and forming a gate contact connected to the gate structure through the silicide layer.
Chen discloses forming a drain contact (Fig. 1I, 134; ¶38) but is silent on the details of subsequent processes. One of ordinary skill in the art would form contacts to the source and gate for completing the device.
Yu discloses a gate structure comprising S/D contacts (Fig. 4,83;¶64) penetrating protective layers (Fig. 4, 662/672;¶58) the gate contact (Fig. 4,83;¶64) connected (electrically) to the gate (Fig. 4,754;¶47) through a silicide layer (Fig. 4,758;¶47)
Before the effective filing date, it would have been obvious to one having ordinary skill in the art to connect the source, drain, and gate to contact plugs for coupling the device to secondary memory circuits and peripheral electronics.
Regarding claim 14, Chen in view of Yu discloses the method according to claim 13, further comprising forming a memory device (Fig. 1I, 119; ¶33 Chen) connected to the drain (Fig. 1I, 126; ¶35 Chen) portion through the drain contact. (Fig.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US-20060019445-A1; Chen) in view of Yu et al. (US-20190214344-A1; Yu) and further in view of Lin et al. (US-20230136441-A1; Lin ).
Regarding claim 15, Chen in view of Yu discloses the method according to claim 14, wherein the memory device is a resistive random-access memory device.
Chen’s memory device is non-volatile. A RRAM device is also non-volatile. Chen’s device is capable of being utilized in a RRAM configuration.
Lin discloses a RRAM device comprising a S/D and gate plugs connected to transistors. (Fig. 1, 22b/26b/24b; ¶21)
It would have been obvious to one having ordinary skill in the art to use the device of Chen in a RRAM device in pursuit of mall memory cell size, ultra-high-speed operation, low-power operation, high endurance.
Allowable Subject Matter
Claim 16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
The relevant art (US-20190214344-A1, US-20150050787-A1, WO-2007138646-A1) discloses a gate structure comprising sidewall spacers, silicide formed of the gate layer and on source/drain region, a protective coating layer over the gate structure and source/drain, contact openings formed over the gate structure and source/drain, filling the openings with conductive material that contacts the gate and source/drain. The art is silent on the limitations cited below in combination with the rest of the claimed limitations. The art discloses contacts extending into silicide layers but not into interior source/drain regions.
Regarding claim 16, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein each of the source contact and the drain contact … extends into an interior of a respective one of the source portion and the drain portion.”, as recited in Claim 16, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 1-9, 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
The relevant art (US-20190214344-A1, US-20150050787-A1, WO-2007138646-A1) discloses a gate structure comprising sidewall spacers, silicide formed of the gate layer and on source/drain region, a protective coating layer over the gate structure and source/drain, contact openings formed over the gate structure and source/drain, filling the openings with conductive material that contacts the gate and source/drain. The art is silent on the limitations cited below in combination with the rest of the claimed limitations. The art discloses contacts extending into silicide layers but not into interior source/drain regions.
Regarding claim 1, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " a minimal width of the opening being the same as a width of the gate structure”, as recited in Claim 1, with the remaining features.
Regarding claim 17, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " a source contact and a drain contact which extend into an interior of to the source portion and an interior of the drain portion, respectively;”, as recited in Claim 17, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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