DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Claims 18-20 have been cancelled; claims 21-23 have been newly added; and claims 1-17 and 21-23 are currently pending.
Information Disclosure Statement
The information disclosure statements filed on 3/11/2025 and 4/24/2025 have been acknowledged and signed copies of the PTO-1449 are attached herein.
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-17, in the reply filed on 7/13/2026 is acknowledged.
Claims 18-20 have been withdrawn and cancelled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/13/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 and 22-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claim 2, the claim recites “the second portion” and “the first portion” in lines 1 and 3 respectively. There is insufficient antecedent basis for these limitations in the claim.
In regards to claims 22 and 23, the claim recites “the first electrical/physical characteristic” in line 2 and “the second electrical/physical characteristic” in line 4. There is insufficient antecedent basis for these limitations. Claim 21 recites “a first electrical characteristic or a first physical characteristic” and “a second electrical characteristic or a second physical characteristic” as separate alternatives, does not recite any “electrical/physical characteristic.”
Claims 3-11 are also rejected for the same reason as they directly or indirectly depend on claim 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-14, 17 and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2023/0043443 A1, hereinafter “Chang”) in view of Yang et al. (US 2022/0319583 A1, hereinafter “Yang”).
In regards to claim 1, Chang discloses (See, for example, Figs. 1-2) a memory device, comprising:
a memory array (104) including a plurality of memory cells (103), each of the memory cells (103) including an access transistor (204) and a fuse resistor (202) coupled to each other in series (See Fig. 2);
a first driver circuit (102) disposed next to the memory array (100) along a first lateral direction (See, the direction that the word lines are arranged, horizontally) and operatively coupled to the access transistor of each of the memory cells (“SRAM arrays that are controlled via bit lines and word lines”, Abstract; “Each of the memory cells 103 is coupled to the controller 102 by at least one of the word lines, at least one of the source lines, and at least one of the bit lines.”, See Par [0019]; and
a second driver circuit (102) disposed next to the memory array (104) along a second lateral direction (See, the direction that the bit lines are arranged, vertically) and operatively coupled to the fuse resistor (202) of each of the memory cells (103, See also Par [0019]);
wherein the access transistors (302) of the memory cells belonging to at least a first one of the plurality of portions have a first electrical characteristic or are disposed along a major surface of a substrate (350);
wherein the access transistors (304) of the memory cells belonging to at least a second one of the plurality of portions have a second electrical characteristic different from the first electrical characteristic or are disposed in one or more of a plurality of metallization layers (See, for example, M2 in Fig. 3B; formed over the metallization layers at operation 706, Fig. 7) disposed above the major surface of the substrate (350).
Chang is silent about wherein the memory array consists of a plurality of portions; and wherein the first electrical characteristic includes at least one of: a first gate dielectric thickness, a first doping concentration, a first flat band voltage, or a first gate dielectric constant, and the second electrical characteristic includes at least one of: a second gate dielectric thickness, a second doping concentration, a second flat band voltage, or a second gate dielectric constant.
Yang while disclosing semiconductor devices teaches (See, for example, fig. 9) a memory cell array that is partitioned into a plurality of portions defined by the distance from the driving circuitry (memory cell array 1000 including regions I, II, and III adjacent to bias source 1002. See Pars [0039] and [0040]); and wherein the first electrical characteristic includes at least one of: a first gate dielectric thickness, a first doping concentration, a first flat band voltage, or a first gate dielectric constant, and the second electrical characteristic includes at least one of: a second gate dielectric thickness, a second doping concentration, a second flat band voltage, or a second gate dielectric constant (“to remedy the increased fail bit count due to voltage drop along bit line (or bit line bar)….SRAM array with more than one region and SRAM cells in different regions have different threshold voltages.” See Par [0039]; and “In terms of threshold voltage, the threshold voltage of the p-type pull-up transistors in region I is greater than the threshold voltage of the p-type pull-up transistors in region II, and the threshold voltage of the p-type pull-up transistors in region II is greater than the threshold voltage of the p-type pull-up transistors in region III.”, See Par [0040]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the eFuse memory array of Chang by partitioning the array into a plurality of portions and providing the access transistors of the respective portions with different electrical characteristics as taught by Yang because partitioning the array into regions having progressively lower threshold voltages with increasing distance from the bias source flattens the fail bit count across the array and improves yield.
In regards to claim 12, Chang discloses (See, for example, Figs. 1-2) a memory device, comprising:
a plurality of one-time-programming (OTP) memory cells (See, Par [0015]);
a first driver circuit (112/114, 102) disposed next to the first portion along a first lateral direction, wherein the first portion is interposed between the second portion (“eFuse memory array is typically connected to peripheral circuits…that provide bias voltages to a bit line during a programming or reading process. Because these peripheral circuits are also formed laterally from the eFuse memory array…”, See Par [0016]) and the first driver circuit (112/114, 102) along the first lateral direction (horizontal); and
a second driver circuit (116/118, 102) disposed next to both of the first and second portions along a second lateral direction (vertical) perpendicular to the first lateral direction (horizontal);
Chang is silent about
a plurality of one-time-programming (OTP) memory cells grouped at least into a first portion and a second portion,
wherein the first and second portions are disposed next to each other along a first lateral direction; and
wherein the OTP memory cells of the first portion are associated with a first electrical/physical characteristic and the OTP memory cells of the second portion are associated with a second electrical/physical characteristic, in which the first electrical/physical characteristic is different from the second electrical/physical characteristic.
Yang discloses (See, for example, Fig. 9) a plurality of one-time-programming (OTP) memory cells grouped at least into a first portion (Region I) and a second portion (Region II),
wherein the first (region I) and second (region II) portions are disposed next to each other along a first lateral direction (horizontal); and
wherein the OTP memory cells of the first portion (region I) are associated with a first electrical/physical characteristic (“SRAM cells in different regions have different threshold voltages”, See Par [0039]) and the OTP memory cells of the second portion (region II) are associated with a second electrical/physical characteristic (“SRAM cells in different regions have different threshold voltages”, See Par [0039]), in which the first electrical/physical characteristic is different from the second electrical/physical characteristic (“to remedy the increased fail bit count due to voltage drop along bit line (or bit line bar)….SRAM array with more than one region and SRAM cells in different regions have different threshold voltages.” See Par [0039]; and “In terms of threshold voltage, the threshold voltage of the p-type pull-up transistors in region I is greater than the threshold voltage of the p-type pull-up transistors in region II, and the threshold voltage of the p-type pull-up transistors in region II is greater than the threshold voltage of the p-type pull-up transistors in region III.”, See Par [0040])..
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the eFuse memory array of Chang by partitioning the array into a plurality of portions and providing the access transistors of the respective portions with different electrical characteristics as taught by Yang because partitioning the array into regions having progressively lower threshold voltages with increasing distance from the bias source flattens the fail bit count across the array and improves yield.
In regards to claim 21, Chang discloses (See, for example, Figs. 1-2) a memory device, comprising:
a plurality of one-time-programming (OTP) memory cells (See, Par [0015]);
a driver circuit (102) disposed next to the first portion along the first lateral direction, wherein the first portion is interposed between the second portion and the driver circuit (102) along the first lateral direction (“eFuse memory array is typically connected to peripheral circuits…that provide bias voltages to a bit line during a programming or reading process. Because these peripheral circuits are also formed laterally from the eFuse memory array…”, See Par [0016]); and
wherein each of the OTP memory cells includes an access transistor (204) and a fuse resistor (202) coupled to each other in series (See, Fig. 2).
Chang is silent about a plurality of one-time-programming (OTP) memory cells grouped at least into a first portion and a second portion, wherein the first portion and the second portion are disposed next to each other along a first lateral direction; and wherein the access transistors of the OTP memory cells of the first portion are associated with a first electrical characteristic or a first physical characteristic, and the access transistors of the OTP memory cells of the second portion are associated with a second electrical characteristic different from the first electrical characteristic or a second physical characteristic different from the first physical characteristic.
Yang discloses (See, for example, Fig. 9) a plurality of one-time-programming (OTP) memory cells grouped at least into a first portion (Region I) and a second portion (Region II),
wherein the first (region I) and second (region II) portions are disposed next to each other along a first lateral direction (horizontal); and
wherein the access transistors of the OTP memory cells of the first portion (region I) are associated with a first electrical/physical characteristic (“SRAM cells in different regions have different threshold voltages”, See Par [0039]) and the access transistors of the OTP memory cells of the second portion (region II) are associated with a second electrical/physical characteristic (“SRAM cells in different regions have different threshold voltages”, See Par [0039]), in which the first electrical/physical characteristic is different from the second electrical/physical characteristic (“to remedy the increased fail bit count due to voltage drop along bit line (or bit line bar)….SRAM array with more than one region and SRAM cells in different regions have different threshold voltages.” See Par [0039]; and “In terms of threshold voltage, the threshold voltage of the p-type pull-up transistors in region I is greater than the threshold voltage of the p-type pull-up transistors in region II, and the threshold voltage of the p-type pull-up transistors in region II is greater than the threshold voltage of the p-type pull-up transistors in region III.”, See Par [0040])..
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to modify the eFuse memory array of Chang by partitioning the array into a plurality of portions and providing the access transistors of the respective portions with different electrical characteristics as taught by Yang because partitioning the array into regions having progressively lower threshold voltages with increasing distance from the bias source flattens the fail bit count across the array and improves yield.
In regards to claim 2, Chang as modified above discloses (See, for example, Fig. 9, Yang) that the second portion (II) is disposed next to the first driver circuit (1002) along the first lateral direction or next to the second driver circuit along the second lateral direction, with the first portion (I) interposed therebetween.
In regards to claim 3, Chang as modified above discloses (See, for example, Fig. 9, Yang) the first electrical characteristic results in a first threshold voltage and the second electrical characteristic results in a second threshold voltage, and wherein the first threshold voltage is higher than the second threshold voltage (See, for example, Claim 1; and Pars [0039] and [0040]).
In regards to claim 7, Chang as modified above discloses (See, for example, Fig. 9, Yang) the access transistors of the memory cells belonging to a third one of the plurality of portions have a third electrical characteristic different from any of the first or second electrical characteristic (“the multi-region SRAM array 1000 includes three regions, each of which have different threshold voltages and alpha ratios.”, Par [0039]).
In regards to claim 8, Chang as modified above discloses (See, for example, Fig. 9, Yang) the third portion (Region III) is disposed next to the first driver circuit (Region I) along the first lateral direction, with the second portion (Region II) interposed therebetween.
In regards to claim 9, Chang as modified discloses (See, for example, Fig. 9, Yang) the first electrical characteristic results in a first threshold voltage (the threshold voltage of the transistor in region I), the second electrical characteristic results in a second threshold voltage (the threshold voltage of the transistor in region II), and the third electrical characteristic results in a third threshold voltage (the threshold voltage of the transistor in region III), and wherein the first threshold voltage is higher than the second threshold voltage and the second threshold voltage is higher than the third threshold voltage (See, for example, Par [0040], “the threshold voltage of the p-type pull-up transistors in region I is greater than the threshold voltage of the p-type pull-up transistors in region II, and the threshold voltage of the p-type pull-up transistors in region II is greater than the threshold voltage of the p-type pull-up transistors in region III.”).
In regards to claims 10 and 17, Chang as modified above discloses (See, for example, Fig. 9, Yang) that the array may include two, three, four, or five regions (See, Par [0039]).
Chang as modified above is silent to any required region size, such that regions of equal size.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have the regions of equal size are among a finite number of identified, predictable configurations. Selecting equal -sized portions, or a first portion equal to or larger than the second portion, amounts to a matter of obvious design choice arrived at through routine engineering, absent a showing of criticality or unexpected result. See MPEP 2144.04(IV). It has been held that such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In regards to claim 11, Chang as modified above discloses three regions of differing threshold voltage (See, Par [0039], and [0040], Yang) but it does not specify their relative sizes.
It is well understood in the art that transistors having higher threshold voltage exhibit lower
subthreshold leakage current than transistors having a lower threshold voltage, as applicant’s own specification acknowledges at Paragraph [0097]. Allocating a larger area of the array to the higher-threshold voltage portion for the purpose of reducing total array leakage current would therefore have been obvious to one of ordinary skill in the art as predictable application of a known principle to achieve a predictable result. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007); See also MPEP 2143 (I)(D).
In regards to claim 13, Chang as modified above discloses (See, for example, Fig. 9, Yang) the first electrical/physical characteristic (the threshold voltage of the transistor in region I) includes a first threshold voltage of each access transistor of the OTP memory cells of the first portion, and the second electrical/physical characteristic (the threshold voltage of the transistor in region II or III) includes a second threshold voltage of each access transistor of the OTP memory cells of the second portion; and wherein the first threshold voltage is higher than the second threshold voltage (See, for example, Pars [0039] and [0040]; and claim 1).
In regards to claims 14 and 23, Chang as modified above discloses that the first electrical/physical characteristic includes each access transistor of the OTP memory cells of the first portion being formed along a major surface of a substrate (“the access transistor 204 is formed over a major surface of a semiconductor substrate, which is sometimes referred to as part of front-end-of-line (FEOL) processing.”, See Par [0030]) ; and wherein the second electrical/physical characteristic includes each access transistor of the OTP memory cells of the second portion being formed in one or more of a plurality of metallization layers disposed above the major surface of the substrate (“the access transistors 302 and 304 can be formed as back-gate transistors. For example, the gate terminal of the access transistors 302 and 304 can be formed below an active region of the access transistors 302 and 304 such that the source and drain terminals of the access transistors 302 and 304 are formed over the gate terminal. In other words, the gate terminal can be closer to the substrate than the source and drain terminals.”, See Par [0034]; “which allows the back-gate transistor to be formed during a BEOL process”, See Par [0048]; “the fuse resistors 312 and 314 are disposed in the metallization layer M2”, See Par [0039]).
Therefore, it would have been obvious to one having ordinary skill in the art to apply Chang’s BEOL access transistor construction to the remote portion identified by Yang’s and Chang’s FEOL access transistor construction to the near portion because this shortens the conduction path between the fuse resistor and the access transistor for the remote cells and thereby further alleviate the IR drop that Yang identifies as the cause of failed bits in remote array region.
In regards to claim 22, Chang as modified above discloses (See, for example, Fig. 9, Yang) the first electrical/physical characteristic includes a first threshold voltage (the threshold voltage of the transistor in region I) of each access transistor of the OTP memory cells of the first portion, and the second electrical/physical characteristic includes a second threshold voltage (the threshold voltage of the transistor in region II or III) of each access transistor of the OTP memory cells of the second portion; and the first threshold voltage is higher than the second threshold voltage (See, for example, Pars [0039] and [0040]; and claim 1).
Allowable Subject Matter
Claims 4-6 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claims 4 and 15, the prior art of record, taken alone or in combination, fails to teach or reasonably suggest the particular peripheral floor plan arrangement in both claims, in which two distinct classes of circuitry are situated outside of the memory array along one and the same lateral direction in a prescribed order. Specifically, the prior art(s) of record does not teach or suggest a memory device in which a group of input/output circuits, themselves built from transistors formed at the same substrate surface as the access transistors of the near portion of the array, is positioned on the far side of the word line driver circuitry, such that the driver circuitry lies between those input/output circuits and the nearest portion of the memory array as measured along the first lateral direction.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERMIAS T WOLDEGEORGIS whose telephone number is (571)270-5350. The examiner can normally be reached on Monday-Friday 8 am - 5 pm E.S.T..
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERMIAS T WOLDEGEORGIS/Primary Examiner, Art Unit 2893
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