DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/12/26 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 11,735,251).
Regarding claim 11, Yang discloses a memory circuit, comprising: a memory array comprising a plurality of memory cells arranged over a plurality of word lines and along a bit line (see Figure 1, for example); and a controller (see Figure 3, 160) operatively coupled to the memory array and comprising an RC detector (162, 163, etc.); wherein the RC detector is configured to advance a timing for a first tracking signal (at N1, see Figure 4, BLTK) to fall, subsequently to a second tracking signal (WLTK) transitioning to rise (see Figure 4) and prior to a third tracking signal (N2, NBLENB) reaching a high logic state; wherein the first tracking signal is conducted through a first tracking line, the second tracking signal is provided to conduct through a second tracking line, and the third tracking signal is conducted through the second tracking line (see Figure 3).
Regarding claim 12, Yang discloses the memory circuit of claim 11, wherein the second tracking line is configured to mimic each of the word lines (on tWL’s), and the first tracking line is configured to mimic the bit line (see column 7, lines 8+).
Allowable Subject Matter
Claims 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 13, the prior art fails to disclose or reasonably suggest in combination all the features of the claim and intervening claims a first transistor that is diode-connected; a second transistor; and a third transistor; wherein the first to third transistor are coupled to one another in series.
Claims 1-4, 6-10, and 19-21 are allowed.
The following is an examiner’s statement of reasons for allowance: the record makes clear the reasons for allowance—see Applicant’s remarks and prior Interview Summary.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM.
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/DOUGLAS KING/ Primary Examiner, Art Unit 2824