Prosecution Insights
Last updated: April 19, 2026
Application No. 18/410,739

MEMORY DEVICES WITH RC TRACKING AND METHODS FOR OPERATING THE SAME

Non-Final OA §102
Filed
Jan 11, 2024
Examiner
KING, DOUGLAS
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
3 (Non-Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
2y 6m
To Grant
84%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
581 granted / 729 resolved
+11.7% vs TC avg
Minimal +4% lift
Without
With
+4.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
18 currently pending
Career history
747
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
43.1%
+3.1% vs TC avg
§102
30.3%
-9.7% vs TC avg
§112
19.5%
-20.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 729 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/12/26 has been entered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 11,735,251). Regarding claim 11, Yang discloses a memory circuit, comprising: a memory array comprising a plurality of memory cells arranged over a plurality of word lines and along a bit line (see Figure 1, for example); and a controller (see Figure 3, 160) operatively coupled to the memory array and comprising an RC detector (162, 163, etc.); wherein the RC detector is configured to advance a timing for a first tracking signal (at N1, see Figure 4, BLTK) to fall, subsequently to a second tracking signal (WLTK) transitioning to rise (see Figure 4) and prior to a third tracking signal (N2, NBLENB) reaching a high logic state; wherein the first tracking signal is conducted through a first tracking line, the second tracking signal is provided to conduct through a second tracking line, and the third tracking signal is conducted through the second tracking line (see Figure 3). Regarding claim 12, Yang discloses the memory circuit of claim 11, wherein the second tracking line is configured to mimic each of the word lines (on tWL’s), and the first tracking line is configured to mimic the bit line (see column 7, lines 8+). Allowable Subject Matter Claims 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 13, the prior art fails to disclose or reasonably suggest in combination all the features of the claim and intervening claims a first transistor that is diode-connected; a second transistor; and a third transistor; wherein the first to third transistor are coupled to one another in series. Claims 1-4, 6-10, and 19-21 are allowed. The following is an examiner’s statement of reasons for allowance: the record makes clear the reasons for allowance—see Applicant’s remarks and prior Interview Summary. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DOUGLAS KING/ Primary Examiner, Art Unit 2824
Read full office action

Prosecution Timeline

Jan 11, 2024
Application Filed
Jul 22, 2025
Non-Final Rejection — §102
Oct 17, 2025
Response Filed
Nov 12, 2025
Final Rejection — §102
Dec 08, 2025
Interview Requested
Dec 16, 2025
Examiner Interview Summary
Dec 16, 2025
Applicant Interview (Telephonic)
Jan 12, 2026
Response after Non-Final Action
Jan 21, 2026
Request for Continued Examination
Jan 28, 2026
Response after Non-Final Action
Jan 30, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603139
NON-VOLATILE MEMORY WITH HIGH PERFORMANCE READ
2y 5m to grant Granted Apr 14, 2026
Patent 12592267
MAGNETORESISTIVE MEMORY DEVICE AND METHOD OF OPERATING SAME USING PHASE CONTROLLED MAGNETIC ANISOTROPY
2y 5m to grant Granted Mar 31, 2026
Patent 12592291
NON-VOLATILE MEMORY WITH IN-PLACE ERROR UPDATING AND CORRECTION
2y 5m to grant Granted Mar 31, 2026
Patent 12579422
INPUT CIRCUITRY FOR ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
2y 5m to grant Granted Mar 17, 2026
Patent 12567455
REFERENCE POTENTIAL GENERATING CIRCUIT AND CONTROL METHOD THEREOF
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
84%
With Interview (+4.2%)
2y 6m
Median Time to Grant
High
PTA Risk
Based on 729 resolved cases by this examiner. Grant probability derived from career allow rate.

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