DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 4-6, 11-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mandalapu et al. (US 2019/0326252) and further in view of Suthram et al. (US 2023/0420432); Suzuki et al. (WO 2008054014A1).
With respect to claims 1, 2, Mandalapu describes a method comprising: providing a firs device wafer 102 (e.g. die) having integrated circuit including conductive feature die 110 within dielectric layer 106 or claimed first dielectric layer with the sides of feature die 110 covered by the dielectric layer 106; planarizing the dielectric layer 106 to form planarized surface 108 by CMP, dry or wet etching (para 30, 33, 34), fig. 1:
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; providing a second feature die 312 of a second singulated die 302, covered by a dielectric layer 106” or claimed second dielectric layer with the sides of features 312 covered by the dielectric layer 106, and “forming a highly planar surface topology, comprising an insulating layer 106” over a base layer 104”, as described above” (para 48); which would be the same method as forming the planar surface 106 by CMP, dry or wet etching; bonding the planar surface 106 of the first wafer or die 102 to the second planar surface 106” of the second singulated die 302 to form a stacked die (fig. 3J):
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Unlike claimed invention, Mandalapu doesn’t specify that the features 110 and 312 of integrate circuit of device dies 102 and 302 comprise optical component of a 3D photonic integrated circuit. However, such 3D die structures are known as shown here by Suthram who teaches stacked dies having optical structures of a photonic IC having conductive traces in a dielectric material (abs.; para 91-93; fig. 1-2). It would have been obvious to one skilled in the art before the effective filing date of the invention to provide IC dies comprising optical component in light of Suthram because they are known structures to form IC package for an electronic system (Suthram, para 2) with expected results.
Unlike claimed invention, Mandalapu doesn’t teach planarizing the dielectric 106 with a location specific ion beam planarizing technique. However, such technique is known and practiced by one skilled in the art as taught by Suzuki, who teaches using gas ion beams to planarize a solid surface by irradiating the surface with the ion beams (abs.; claims 1-9) where the surface is scanned with a scanning mechanism (page 8), which provide a location specific ion beam planarizing process. It would have been obvious for one skilled in the art before the effective filing date of the invention to planarize the dielectric layer 106 with the gas ion beam process in light of Suzuki because Mandalapu teaches to planarize the dielectric layer 106 using dry process (para 34) and using known technique without changes in their respective functions, in the case using dry process such as gas ion beam process to planarize the dielectric layer surface, would provide a planar surface with expected results.
With respect to claim 13, in the combined methods of Mandalapu, Suthram and Suzuki above, Mandalapu further shows in fig. 3J the structure die of conductive feature 312 which is larger than the structure die containing the conductive feature 110 or claimed the first die being larger than the second die. The gas ion beam would provide locally planarizing portion of the surfaces of the die 110 and 312 as it scans through the surface of the dies and planarizes a portion at a time across the surface.
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With respect to claim 4, Mandalapu, in figure 3J above, shows a die (102) to die (312) bonding with direct bonding (para 6).
With respect to claims 5, 12, 17 the Mandalapu describes “bonding surfaces are arranged and aligned so that the conductive interconnect structures from the respective surfaces are joined during the bonding. The joined interconnect structures form continuous conductive interconnects (for signals, power, etc.) between the stacked dies or wafers.” With the combined teaching of Mandalupu and Suthram’s stacked dies having optical structures of a photonic IC, the resulted structure would provide 3D stacked PiC die comprises an optical coupler coupling the first PIC die of 102 to the second PIC die of 312, the optical coupler would comprises a portion of the first optical component of the first PIC 102 and a portion of the second optical component of the second PIC die 312 and also the first planarized surface to the second planarized surface forms an optical coupler comprising an overlapping portion of the first optical component and the second optical component.
With respect to claims 6, 18 the first planarized surface includes a metal 110 and a dielectric 106 and the second planarized surface comprises a second metal 110’ or 312 and a second dielectric 106’ (para 32, 33, 41) wherein a hybrid bonding technique is used (para 6, 24, 44) attaching the first metal 110 with the second metal 110’ or 312 and the first dielectric layer 106 with the second dielectric layer 106’ (fig. 3J).
With respect to claim 11, Suthram further teaches the interconnect stacks include optical waveguides (para 44, 97-99).
With respect to claims 14-16, please see rejections of claims 1 and 2 above where the combined method of Mandalapu, Suthram and Suzuki would provide the steps of planarizing the surfaces of the dies with first and second optical components with the gas cluster ion beam before the bonding process.
Allowable Subject Matter
Claims 3, 7, 8, 9, 10, 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3 is allowed over the applied prior art, because Mandalapu, while describes providing structures with planarized dies; however, he doesn’t teach performing a singulation process to form the first die prior to performing the location specific ion beam planarizing. He teaches singulating dies 302 after it has been prepared with a planarizing step (para 41, 45).
Claim 7 and its dependent claim 8 are allowed over the applied prior art, because the combined method of Mandalapu and Suzuki, while suggest using a location specific ion beam planarizing technique; however, fail to teach further steps of compiling a first die map of a thickness of the first dielectric layer; configuring an ion beam etcher to perform a first process, the first process having a beam location dependent etch rate of the first dielectric layer, the etch rate based on the first die map; and performing the first process to remove a portion of the first dielectric layer.
Claim 9 is allowed over the applied prior art, because Mandalapu doesn’t teach performing a touchup etch to remove a damage layer formed during the ion beam planarization, the touchup etch comprising a wet etch or a chemical mechanical polishing process.
Claim 10 is allowed over the applied prior art, because Mandalapu doesn’t teach after planarizing, a total thickness variation (TTV) of a thickness of the first dielectric layer covering the first optical component is less than 2 nm and greater than 0.5 nm; and wherein, after planarizing, a TTV of a thickness of the second dielectric layer covering the second optical component is less than 2 nm and greater than 0.5 nm.
Claim 19 is allowed over the applied prior art, because Mandalapu doesn’t teach the steps of the locally planarizing comprising obtaining a surface topography map of the portion of the major surface of the first die and based on the surface topography map setting a scan rate of the ion beam to obtain the planarized surface.
Claims 20-25 are allowed over the applied prior art because the combined method of Mandalupu, Suthram and Suzuki, while suggest using a location specific ion beam process to provide a planarized surface; however, fail to suggest the steps of performing a location specific ion beam process to form a recess into a major surface of the first die, the performing comprising scanning a portion of the major surface relative to a ion beam to form the recess having a planarized bottom surface; and attaching the second die to the planarized bottom surface of the recess.
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/DUY VU N DEO/Primary Examiner, Art Unit 1713
2/23/2026