Prosecution Insights
Last updated: July 17, 2026
Application No. 18/411,041

SEMICONDUCTOR PACKAGE COMPONENT AND METHOD FOR FORMING THE SAME

Non-Final OA §102§103
Filed
Jan 12, 2024
Examiner
BOOTH, RICHARD A
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
901 granted / 1052 resolved
+17.6% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
38 currently pending
Career history
1089
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
83.3%
+43.3% vs TC avg
§102
6.2%
-33.8% vs TC avg
§112
3.5%
-36.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1052 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of group II in the reply filed on 03/08/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 17-18, 27-29, 31-34, and 36 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Burbach et al., US 2006/0046400. Burbach et al. shows the invention as claimed including a method comprising: Forming a conductive feature (12,24); Forming a tensile-stressed layer 201 over the conductive feature; Forming a compressive-stressed layer 203 over the tensile-stressed layer; Forming a dielectric layer 204 over the compressive-stressed layer; Exposing a portion of a top surface of the conductive feature (see fig. 2E); and Forming a conductor over the exposed portion of the conductive feature (see paragraph 0061 and figs.2a-2e and paragraphs 0033-0068 for description of entire process). Regarding the method being for forming a semiconductor package component, note that this limitation in the preamble is not given patentable weight because If the body of a claim fully and intrinsically sets forth all of the limitations of the claimed invention, and the preamble merely states, for example, the purpose or intended use of the invention, rather than any distinct definition of any of the claimed invention’s limitations, then the preamble is not considered a limitation and is of no significance to claim construction. Shoes by Firebug LLC v. Stride Rite Children’s Grp., LLC, 962 F.3d 1362, 2020 USPQ2d 10701 (Fed. Cir. 2020) (see MPEP 2111.02). With respect to dependent claims 18 and 28, note that Burbach et al. discloses that the tensile-stressed layer and the compressive-stressed layer comprise a same silicon nitride material (see paragraphs 0036 and 0044). As to independent claim 27, note that Burbach et al. shows the invention as claimed including a method for forming a semiconductor component, comprising: Forming a conductive feature (12,24); Forming a tensile-stressed layer 201 over the conductive feature; Forming a first dielectric layer 202 over the tensile-stressed layer; Forming a compressive-stressed layer 203 over the first dielectric layer; Forming a second dielectric layer 204 over the compressive-stressed layer; and Forming a conductor over the second dielectric layer and coupled to the conductive feature (see paragraph 0061 and figs.2a-2e and paragraphs 0033-0068 for description of entire process). Concerning dependent claim 29, Burbach et al. discloses where the first dielectric material 202 is silicon oxide (see paragraph 0038) and the tensile stressed layer is silicon nitride (see paragraph 0036). With respect to dependent claim 31, note that when giving the claim its broadest reasonable interpretation, the compressive stressed layer 203 can be split in two and considered to be a first dielectric layer with a compressive stress and an overlying compressive-stressed layer. As to dependent claim 32, note that the first dielectric layer 202 is free of stress. With respect to independent claim 33, note that Burbach et al. shows the invention as claimed including a method of forming a component comprising: Forming a conductive feature (12,24); Forming a first tensile-stressed layer (lower half of layer 201) over the conductive feature; Forming a second tensile-stressed layer (upper half of layer 201) over the first tensile-stressed layer; Forming a first dielectric layer 202 over the tensile-stressed layer; Forming a compressive-stressed layer 203 over the first dielectric layer; Forming a second dielectric layer 204 over the compressive-stressed layer; and Forming a conductor over the second dielectric layer and coupled to the conductive feature (see paragraph 0061 and figs.2a-2e and paragraphs 0033-0068 for description of entire process). Concerning dependent claim 34, note that Burbach et al. discloses wherein the first tensile-stressed layer and the second tensile-stressed layer comprise a same material. As to dependent claim 36, note that when giving the claim its broadest reasonable interpretation, the first tensile-stressed layer can be selected in such a way so that it is greater than a thickness of the second tensile-stressed layer. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 19-26 and 30-31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Burbach et al., US 2006/0046400. Burbach et al. is applied as above and additionally discloses forming the tensile and compressive layers using plasma enhanced chemical vapor deposition but does not expressly disclose processing parameters such as the RF power used when making the layers. However, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to determine through routine experimentation the optimum RF energy during plasma deposition depending upon a variety of factors including the desired film density and adhesion and such limitation would not lend patentability to the instant application absent a showing of unexpected results. Concerning dependent claim 21, Burbach et al. is applied as above but does not expressly disclose wherein a thickness of the tensile-stressed layer is equal to a thickness of the compressive-stressed layer. However, the thicknesses of the tensile-stressed layer 201 and compressive-stressed layer overlap (see paragraphs 0035 and 0046). Therefore, a prima facie case of obviousness exists because overlapping ranges establish a prima case of obviousness (see MPEP 2144.05). Furthermore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to determine through routine experimentation the optimum thickness of the tensile and compressively strained layers depending upon a variety of factors including the overall desired stress levels and such limitation would not lend patentability to the instant invention absent a showing of unexpected results. Concerning dependent claim 22, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to form the claimed second conductive feature, for example, in order to have a multi-level metallization configuration that is well known in the art. As to dependent claims 23-26 and 30, Burbach et al. does not expressly disclose the claimed thickness of the tensile-stressed layer. However, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to determine through routine experimentation the optimum thickness of the tensile-stressed layer depending upon a variety of factors in including the desired overall stress of the dielectric layers and such limitation would not lend patentability to the instant invention absent a showing of unexpected results. Claim(s) 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Burbach et al., US 2006/0046400 in view of Crook et al., U.S. Patent 9,472,610. Burbach et al. is applied as above but does not expressly disclose where a tensile stress of the second tensile-stressed layer is less than a tensile stress of the first tensile-stressed layer. However, Crook et al. discloses changing the particular values of a stressed film by changing processing parameters during formation of the layer (see, for example, col. 7-line 6 to col. 8-line 34). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to form the second tensile-stressed layer less than a tensile stress of the first tensile-stressed layer in order to provide an effective transition to the overlying layer. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2019/0067187 discloses dielectric layers separating conductive features that contact each other (see abstract). Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RICHARD A BOOTH/ Primary Examiner, Art Unit 2812 May 23, 2026
Read full office action

Prosecution Timeline

Jan 12, 2024
Application Filed
May 29, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+8.4%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1052 resolved cases by this examiner. Grant probability derived from career allowance rate.

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