CTNF 18/411,226 CTNF 100778 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Information Disclosure Statement The information disclosure statements (IDS) submitted on 01/12/2024 and 04/14/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim s 1-3, 5-7, 9, 11-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US20220384609A1; Lin et al.; (hereinafter “Lin”) in view of US20200066880A1; Chang et al.; (hereinafter “Chang”) . Regarding Claim 1 , Lin teaches a method for forming a semiconductor device structure (Figure 19), comprising: forming a metal gate stack (#1602) wrapped around a plurality of semiconductor nanostructures (#306), wherein the metal gate stack has a gate dielectric layer (#1604) and a gate electrode (#1606), and the semiconductor nanostructures are adjacent to an epitaxial structure (#1202, [0034]); forming a protective structure (#1302/#1304) over the epitaxial structure (#1202), wherein the protective structure laterally surrounds the protruding portion of the gate electrode (#1302/#1304 surrounds #1606); and forming a conductive contact (#1904) electrically connected to the epitaxial structure (#1202) and penetrating through the protective structure (#1302/#1304). Lin does not explicitly teach recessing the gate dielectric layer, wherein a protruding portion of the gate electrode protrudes from a top surface of the gate dielectric layer after the gate dielectric layer is recessed. However, Chang teaches a method for forming a semiconductor structure ([0014]) comprising recessing the gate dielectric layer, wherein a protruding portion of the gate electrode protrudes from a top surface of the gate dielectric layer after the gate dielectric layer is recessed (Figure 1J, gate dielectric #134’ is recessed and gate electrode #138 protrudes from top surface of #134’). It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin with the teaching of Chang in order to prevent short circuit between the gate dielectric layer and nearby conductive feature according to Chang, [0052]. Regarding Claim 2 , Lin in view of Chang teaches the method for forming a semiconductor device structure as described in claim 1, wherein Lin further teaches: forming a dielectric layer (#1702, Figure 17) over the metal gate stack (#1602), the protective structure (#1302/#1304), and the epitaxial structure (#1202); forming a contact opening (#1802, Figure 18) in the dielectric layer (#1702); forming a protective layer (#1302/#1304) over sidewalls of the contact opening (#1802); partially removing the protective structure to expose the epitaxial structure after the protective layer is formed (#1302-#1304 are partially removed to expose epitaxial drain #1202); and forming the conductive contact (#1904, Figure 19) such that at least a portion of the conductive contact is in the contact opening (#1802). Regarding Claim 3 , Lin in view of Chang teaches the method for forming a semiconductor device structure as described in claim 2, wherein Lin further teaches deepening the contact opening so that the contact opening extends into the epitaxial structure after the formation of the protective layer (Figure 18-19, [0049], opening #1802 extends for formation of silicide features #1902). Regarding Claim 5 , Lin in view of Chang teaches the method for forming a semiconductor device structure as described in claim 3, wherein Lin further teaches forming a metal-semiconductor compound element (#1902, Figure 19, [0049]) on the epitaxial structure (#1202), wherein the metal-semiconductor compound element (#1902) is between the conductive contact (#1904) and the epitaxial structure (#1202). Regarding Claim 6 , Lin in view of Chang teaches the method for forming a semiconductor device structure as described in claim 5, wherein Lin further teaches the metal-semiconductor compound element is separated from the protective layer by the protective structure (Figure 19, silicide feature #1902 is separated from dielectric layer #1304 by dielectric layer #1302). Regarding Claim 7 , Lin in view of Chang teaches the method for forming a semiconductor device structure as described in claim 1, wherein Lin further teaches: forming a fin structure (#402, Figure 7) over a substrate (#300), wherein the fin structure has a plurality of semiconductor layers (#306) and a plurality of sacrificial layers (#304) laid out in an alternating manner; forming a dummy gate stack (#612) extending across the fin structure (402); partially removing the fin structure (Figure 9) to form a recess (#902) exposing side surfaces of the semiconductor layers (#306) and the sacrificial layers (#304); forming the epitaxial structure (#1202, Figure 12) in the recess; forming a second dielectric layer (#1302/#1304) laterally surrounding the epitaxial structure (#1202) and the dummy gate stack (#612); and removing the dummy gate stack (#612, Figures 13-14) and the sacrificial layers (#304), wherein remaining portions of the semiconductor layers form the semiconductor nanostructures (#306). Regarding Claim 9 , Lin in view of Chang teaches the method for forming a semiconductor device structure as described in claim 1. Lin does not teach the protective structure is formed to be in direct contact with the gate electrode and the gate dielectric layer. However, Chang teaches the protective structure is formed to be in direct contact with the gate electrode and the gate dielectric layer (Figure 1L, [0049], hard mask #152 contacts gate dielectric #134’ and gate electrode #138’). It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin with the teaching of Chang for reason set forth in rejection of claim 1. Regarding Claim 11 , Lin teaches a method for forming a semiconductor device structure (Figure 19), comprising : forming a metal gate stack (#1602) extending across a semiconductor nanostructure (#306), wherein the metal gate stack has a gate dielectric layer (#1604) and a gate electrode (#1606), and the semiconductor nanostructure is electrically connected to an epitaxial structure (#1202, [0034]); forming a protective structure (#1302/#1304) laterally surrounding the sidewall of the gate electrode (#1606); and forming a conductive contact (#1904) electrically connected to the epitaxial structure (#1202) and penetrating through the protective structure (#1302/#1304). Lin does not explicitly teach removing the gate dielectric layer so that a sidewall of the gate electrode previously covered by the gate dielectric layer is exposed; However, Chang teaches a method for forming a semiconductor structure ([0014]) comprising removing the gate dielectric layer so that a sidewall of the gate electrode previously covered by the gate dielectric layer is exposed (Figure 1J, gate dielectric #134’ is partially recessed and gate electrode #138 is exposed). It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin with the teaching of Chang in order to prevent short circuit between the gate dielectric layer and nearby conductive feature according to Chang, [0052]. Regarding Claim 12 , Lin in view of Chang teaches the method for forming a semiconductor device structure as described in claim 11, wherein Lin further teaches: forming a dielectric layer (#1702, Figure 17) over the metal gate stack (#1602), the protective structure (#1302/#1304), and the epitaxial structure (#1202); partially removing the dielectric layer (#1702, Figure 18) to form an opening (#1802) exposing the protective structure (#1302/#1304); forming a protective layer (#1302/#1304) over sidewalls and a bottom of the opening (#1802); partially removing the protective layer and the protective structure to expose the epitaxial structure (#1302-#1304 are partially removed to expose epitaxial drain #1202; and forming the conductive contact (#1904, Figure 19) electrically connected to the epitaxial structure (#1202). Regarding Claim 13 , Lin in view of Chang teaches the method for forming a semiconductor device structure as described in claim 12, wherein Lin further teaches partially removing the epitaxial structure after the epitaxial structure is exposed and before the conductive contact is formed (Figure 18-19, [0049], opening #1802 extends for formation of silicide features #1902 before forming drain contact #1904). Regarding Claim 14 , Lin in view of Chang teaches the method for forming a semiconductor device structure as described in claim 11, wherein Lin further teaches forming a metal-semiconductor compound element (#1902, Figure 19, [0049]) on the epitaxial structure (#1202) before the conductive contact (#1904) is formed, wherein the metal-semiconductor compound element (#1902) is between the conductive contact (#1904) and the epitaxial structure (#1202). Regarding Claim 15 , Lin in view of Chang teaches the method for forming a semiconductor device structure as described in claim 11, wherein Lin further teaches the protective structure (#1302/#1304, Figure 19) is formed to be in direct contact with the epitaxial structure (#1202). Lin does not teach the protective structure is formed to be in direct contact with the gate electrode and the gate dielectric layer. However, Chang teaches the protective structure is formed to be in direct contact with the gate electrode and the gate dielectric layer (Figure 1L, [0049], hard mask #152 contacts gate dielectric #134’ and gate electrode #138’). It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin with the teaching of Chang for reason set forth in rejection of claim 11. Regarding Claim 16 , Lin teaches a semiconductor device structure (Figure 19), comprising: an epitaxial structure (#1202); a semiconductor nanostructure (#306) electrically connected to the epitaxial structure (#1202); PNG media_image1.png 1009 1371 media_image1.png Greyscale a metal gate stack (#1602) extending across the semiconductor nanostructure (#306), wherein the metal gate stack has a gate dielectric layer (#1604) and a gate electrode (#1606); and a protective structure (#1302/#1304) over the metal gate stack (#1602) and the epitaxial structure (#1202), wherein a top of the gate dielectric layer is closer to the semiconductor nanostructure than a top of the metal gate stack (Figure 19 of Lin annotated, a top surface of #1604 is closer to #306 than a top of #1602). Lin does not explicitly teach the top of the gate dielectric layer is between a top surface of the protective structure and a bottom surface of the protective structure. However, Chang teaches a semiconductor structure ([0014]), comprising a top of a gate dielectric layer (#134b’, Figure 4, gate dielectric) is between a top and a bottom surface of a protective structure (#128, ILD layer). It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin with the teaching of Chang, as it would be a simple substitution of one known element (gate structure and dielectric structure of Lin ) for another (gate structure and dielectric structure of Chang ) in comparable device structures to obtain predictable results. See MPEP 2143(I)(B). Regarding Claim 17 , Lin in view of Chang teaches the semiconductor device structure as described in claim 16, wherein Lin further teaches a conductive contact (#1904, Figure 19) electrically connected to the epitaxial structure (#1202), wherein the conductive contact penetrates through the protective structure (#1302/#1304). Regarding Claim 20 , Lin in view of Chang teaches the semiconductor device structure as described in claim 11, wherein Lin further teaches the metal-semiconductor compound element (#1902, Figure 19) is embedded in the epitaxial structure (#1202) . 07-21-aia AIA Claim s 4, 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Chang, and further in view of US20200176597A1; Vellianitis et al.; (hereinafter “Vellianitis”) . Regarding Claim 4 , Lin in view of Chang teaches the method for forming a semiconductor device structure as described in claim 3. Lin in view of Chang do not explicitly teach the contact opening extends downwards across a top of the semiconductor nanostructures after the deepening of the contact opening. PNG media_image2.png 783 624 media_image2.png Greyscale However, Vellianitis teaches a manufacturing process of a gate-all-around FET device ([0034]), comprising the contact opening extends downwards across a top of the semiconductor nanostructures after the deepening of the contact opening (Figure 20B of Vellianitis, conductive contact layer #75 extends across the nanostructures). It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin in view of Chang with the teaching of Vellianitis , as it would be a simple substitution of one known element (contact features of Lin ) for another (contact layer of Vellianitis ) to obtain predictable results. See MPEP 2143(I)(B). Regarding Claim 10 , Lin in view of Chang teaches the method for forming a semiconductor device structure as described in claim 1. Lin in view of Chang do not teach forming a dielectric structure separating the metal gate stack into two separate portions, wherein the dielectric structure penetrates through the protective structure. However, Vellianitis teaches forming a dielectric structure separating the metal gate stack into two separate portions, wherein the dielectric structure penetrates through the protective structure (Figure 20B, a portion of ILD layer #50 extends across gate stack #82-86). It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin in view of Chang with the teaching of Vellianitis by known methods to yield predictable results (implementation of a dielectric layer to insulate the gate structures). See MPEP 2143(I)(A). Regarding Claim 19 , Lin in view of Chang teaches the semiconductor device structure as described in claim 17. Lin in view of Chang do not teach a dielectric structure separating the metal gate stack into two separate portions, wherein the dielectric structure penetrates through the protective structure, and the dielectric structure is in direct contact with the metal gate stack and the protective structure. However, Vellianitis teaches a dielectric structure separating the metal gate stack into two separate portions, wherein the dielectric structure penetrates through the protective structure, and the dielectric structure is in direct contact with the metal gate stack and the protective structure (Figure 20B, a portion of ILD layer #50 extends across gate stack #82-86). It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin in view of Chang with the teaching of Vellianitis by known methods to yield predictable results (implementation of a dielectric layer for insulating the gate structures). See MPEP 2143(I)(A) . 07-21-aia AIA Claim s 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Chang, and further in view of US20190333812A1; Seong et al.; (hereinafter “Seong”) . Regarding Claim 8 , Lin in view of Chang teaches the method for forming a semiconductor device structure as described in claim 7, wherein Lin further teaches: forming gate spacers (#702, Figure 7) over sidewalls of the dummy gate stack (#612) before the epitaxial structure is formed (Figure 12); and partially removing the second dielectric layer (#1302/#1304, Figure 18) after the formation of the metal gate stack (#1602) and before the recessing of the gate dielectric layer (see rejection of claim 1 for recessing the gate dielectric layer, Figure 17, dielectric layer #1702 covers gate structure #1602, hence, #1702 needs to be removed before the gate dielectric layer can be etched). Lin in view of Chang does not explicitly teach partially removing the gate spacers, wherein the gate dielectric layer is partially exposed after the partial removal of the gate spacers and the second dielectric layer. However, Seong teaches a method for fabricating a semiconductor device ([0119]), comprising partially removing the gate spacers (#140, Figures 21-23, spacers), wherein the gate dielectric layer (#120, gate dielectric) is partially exposed after the partial removal of the gate spacers (#140) and the second dielectric layer (#162, etch stop layer). It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin in view of Chang with the teaching of Seong that allows an implementation of an etch stop layer in the recessed area that prevent short-circuit between gate electrode and source/drain contact according to Seong, [0072], see also Figure 12. Regarding Claim 18 , Lin in view of Chang teaches the semiconductor device structure as described in claim 17, wherein Lin further teaches a dielectric layer (#1702, Figure 19) laterally surrounding an upper portion of the conductive contact (#1904). Lin in view of Chang does not explicitly teach a protective layer between the conductive contact and the dielectric layer, wherein the protective layer is separated from the epitaxial structure by the protective structure. However, Seong teaches a protective layer (#175, Figure 13, [0107]) between a conductive contact (#190, contact) and a dielectric layer (#280, ILD layer), wherein the protective layer (#175) is separated from the epitaxial structure (#150, epitaxial source/drain) by the protective structure (#160, etch stop layer). It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Lin in view of Chang with the teaching of Seong in order to efficiently reduce parasitic capacitance or leakage current between the gate electrode and the contact layer according to Seong , [0107] . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US20200365586A1 – Figure 5Q US20220051939A1 – Figures 1-16 US20250107219A1 – Figures 14-16 Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIEN TRAN whose telephone number is (571)272-6967. The examiner can normally be reached Monday-Thursday 9:00 am - 6:00 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE S KIM can be reached on (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TIEN TRAN/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/411,226 Page 2 Art Unit: 2812 Application/Control Number: 18/411,226 Page 3 Art Unit: 2812 Application/Control Number: 18/411,226 Page 4 Art Unit: 2812 Application/Control Number: 18/411,226 Page 5 Art Unit: 2812 Application/Control Number: 18/411,226 Page 6 Art Unit: 2812 Application/Control Number: 18/411,226 Page 7 Art Unit: 2812 Application/Control Number: 18/411,226 Page 8 Art Unit: 2812 Application/Control Number: 18/411,226 Page 9 Art Unit: 2812 Application/Control Number: 18/411,226 Page 10 Art Unit: 2812 Application/Control Number: 18/411,226 Page 11 Art Unit: 2812 Application/Control Number: 18/411,226 Page 12 Art Unit: 2812 Application/Control Number: 18/411,226 Page 13 Art Unit: 2812 Application/Control Number: 18/411,226 Page 14 Art Unit: 2812
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