DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “attaching structure” in claims 8 through 11 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 11-15, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ku et al. (US 2019/0385929 A1).
Regarding claim 1, Ku et al. discloses a semiconductor package structure, comprising:
an interposer substrate (107) formed over a package substrate (103);
a die (115, 117 processor / memory dies) disposed over the interposer substrate;
a first heat spreader (127, thermal conductive ring) disposed over the package substrate (103); and
a second heat spreader (131, VC-Lid) disposed over the die and connected to the first heat spreader,
wherein a coefficient of thermal expansion (CTE) of the first heat spreader and a coefficient of thermal expansion of the second heat spreader are different (Materials of the ring/frame can differ from the VC-Lid (¶ 33, 64) — e.g., copper ring vs. CuW lid — implying different CTEs).
Regarding claim 2, Ku et al. discloses the semiconductor package structure as claimed in claim 1, further comprising: an adhesive layer (third thermal interface material (TIM) 129 (¶ 39–40)) formed between the first heat spreader and the second heat spreader.
Regarding claim 3, Ku et al. the semiconductor package structure as claimed in claim 1, wherein a bottom surface of the second heat spreader is higher than a top surface of the die (VC‑Lid 131 sits on top of TIM 113 over encapsulant/die stack (¶ 40–46); encapsulant and TIM create a vertical separation; the lid’s bottom surface is above the die’s top surface; see Figures (FIG. 1A, FIG. 5) clearly show the lid bottom surface higher than die top surface.
Regarding claim 4, Ku et al. discloses the semiconductor package structure as claimed in claim 1, wherein the first heat spreader comprises an inner portion and an outer portion, wherein the second heat spreader covers the inner portion of the first heat spreader (Thermally conductive ring / VC‑Lid Frame has inner portion facing encapsulant/dies and outer portion facing outward (¶ 59–64); VC‑Lid covers inner portion when assembled (¶ 40–46, FIG. 5)).
Regarding claim 5, Ku et al. discloses the semiconductor package structure as claimed in claim 4, wherein a top surface of the outer portion of the first heat spreader is higher than a top surface of the inner portion of the first heat spreader (In FIG. 5 and related text (¶ 69–71), outer portion can have higher top surface than inner portion — differences in height are described in context of gaps/offsets and geometry).
Regarding claim 6, Ku et al. discloses the semiconductor package structure as claimed in claim 4, wherein a sidewall of the outer portion of the first heat spreader is separated from a sidewall of the second heat spreader (Separation/offset between sidewalls of lid and ring/frame explicitly described (¶ 69–71, distances D1 and D2 between inner/outer sidewalls); Figures show the separation).
Regarding claim 7, Ku et al. discloses the semiconductor package structure as claimed in claim 4, wherein a bottom surface of the outer portion of the first heat spreader is wider than a top surface of the outer portion of the first heat spreader (ring/frame has an L‑shaped cross‑section (¶ 59–64), which inherently means the base (bottom surface) is wider than the top surface).
Regarding claim 8, Ku et al. semiconductor package structure, comprising:
an interposer substrate (107) disposed over a package substrate (103);
a first heat spreader (127, thermally conductive ring) attached to the package substrate (103);
an attaching structure formed over the first heat spreader (the VC‑Lid connects via TIM 129 to the ring/frame — TIM functions as attaching structure. No mechanical protrusion/recess; attachment is thermal adhesive);
a die (115, 117; processor / memory dies) disposed over the interposer substrate; and
a second heat spreader (130) attached to the die and the attaching structure (VC-Lid 131 attached to die via TIM 113 and to ring/frame via TIM 129),
wherein the first heat spreader and the second heat spreader are made of different materials (materials can differ — ring/frame vs. lid (¶¶ 33, 64).
Regarding claim 9, Ku et al. discloses the semiconductor package structure as claimed in claim 8, wherein the attaching structure is in direct contact with the first heat spreader and the second heat spreader (the “attaching structure” between the first heat spreader (thermally conductive ring 127 / VC‑Lid Frame 535) and the second heat spreader (VC‑Lid 131) is the third thermal interface material (TIM) 129 (¶ 39–40); TIM 129 is physically in contact with both the ring/frame and the lid — i.e., direct contact).
Regarding claim 11, Ku et al. discloses the semiconductor package structure as claimed in claim 8, further comprising:
an encapsulating layer surrounding the die (encapsulant 125 surrounds processor/memory dies (¶ 26–27);
a thermal interface material (TIM) covering the die and the encapsulating layer (TIM 113 covers the die and encapsulant (¶ 30, 40–46), wherein a top surface of the thermal interface material is substantially level with a top surface of the attaching structure (TIM 129 (attaching structure) sits on ring/frame; top surfaces of TIM 113 and TIM 129 are at similar heights so lid can seat evenly — this is visible in FIG. 1A and described in ¶ 40–46).
Regarding claim 12, Ku et al. discloses the semiconductor package structure as claimed in claim 8, wherein the second heat spreader has an inner portion and an outer portion, and a bottom surface of the inner portion of the second heat spreader is lower than a bottom surface of the outer portion of the second heat spreader (VC‑Lid geometry: inner portion over encapsulant/die, outer portion over ring/frame; some embodiments, offsets/gaps show inner portion bottom surface lower than outer portion bottom surface (¶¶ 69–71, FIG. 5); this is part of the described height differences to accommodate TIM thickness).
Regarding claim 13, Ku et al. discloses the semiconductor package structure as claimed in claim 8, wherein a sidewall of the second heat spreader is between opposite sidewalls of the first heat spreader (sidewall positioning: distances D1 and D2 between sidewalls of lid and ring/frame (¶¶ 69–71); figures show second heat spreader’s sidewalls located inward from first heat spreader’s outer sidewalls — i.e., between them).
Regarding claim 14, Ku et al. discloses the semiconductor package structure as claimed in claim 8, wherein the first heat spreader comprises an inner portion and an outer portion, and the inner portion of the first heat spreader is thicker than the outer portion of the first heat spreader (Ring/frame geometry: inner portion near cavity can be thicker than outer portion — implied by L‑shaped cross‑section (¶ 59–64); outer portion is narrower at top; inner portion has more vertical material thickness).
Regarding claim 15, Ku et al. discloses a semiconductor package structure, comprising:
a first die (115) and a second die (117) disposed over a package substrate (103);
an encapsulating layer (125) surrounding the first die (115) and the second die (117) (Encapsulant 125 surrounding processor and memory dies (¶ 26–27, FIG. 1A);
a first heat spreader (127) surrounding the encapsulating layer (125) (thermally conductive ring 127 or VC-Lid Frame 535 surrounds encapsulant and dies (¶¶ 31–33, 59–64)); and
a second heat spreader (131) partially overlapping a first top surface of the first heat spreader and exposing a second top surface of the first heat spreader (VC-Lid 131 overlaps ring/frame; gaps/offsets (D1, D2) leave parts of ring/frame exposed (¶¶ 69–71).
Regarding 19, Ku et al. discloses the semiconductor package structure as claimed in claim 15, wherein the first top surface of the first heat spreader is coplanar with the second top surface of the first heat spreader (ring/frame top is presented as a single top plane receiving TIM 129 (FIG. 1A; ¶¶ 39–41); “first” vs “second” top surfaces as different regions of the same ring/frame, they are coplanar in the reference).
Regarding claim 20, Ku et al. discloses the semiconductor package structure as claimed in claim 15, further comprising a thermal interface material (TIM) structure connecting the second heat spreader and the first die and the second die (TIM 113 is formed over and in contact with multiple dies and the encapsulant, and the VC-Lid 131 is placed to thermally couple to TIM 113 (FIG. 1A; ¶¶ 30, 40–46); TIM 113 covers multiple dies and couples them to the integrated VC-Lid (FIGS. 7–13; ¶¶ 80–82, 95).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ku et al.
Regarding claim 10, Ku et al. discloses the semiconductor package structure as claimed in claim 8, but does not specifically disclose that the attaching structure comprises first pad structures formed over the first heat spreader; second pad structures formed under the second heat spreader,
wherein the first pad structures and the second pad structures are bonded to each other.
Ku et al. discloses the connection is via TIM or adhesive, not via bonding pads.
It would have been obvious to one having ordinary skill before the filing date of the invention that a well-known alternative to TIM-based bonding or adhesive bonding would be pad to pad bonding as described in claim 10, using this alternative is within the purview of one having ordinary skill in the art and is often chosen when maximum conductivity and mechanical strength are of concern.
Allowable Subject Matter
Claims 16 to 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The cited prior art, including US 2019/0385929 A1, discloses a package in which a second heat spreader (e.g., a lid) is mounted over a first heat spreader (e.g., a ring/frame) using an intervening interface layer (e.g., TIM/adhesive), with the bottom surface of the second heat spreader at or above the elevation of the top surface of the first heat spreader to receive the TIM. None of the references of record teach or suggest the specific vertical relationships now recited in claims 16–18.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the timing fee set forth in 37 CFR 1.17(p) on January 9, 2026 prompted the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUE A PURVIS whose telephone number is (571)272-1236. The examiner can normally be reached M-F 0830 to 1630.
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/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893 1-2
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