Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In the applicant’s response to election/restriction filed on 06/08/2026, the applicant elected invention I, claims 1-16 without traverse. Additionally, applicant canceled claims 17-20 and added new claims 21-24 which fall under the category of invention I and do not comprise new matter. Thus claims 1-16 and 21-24 will examined upon the merits below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20220344358) in view of Liaw (US 20220336474).
Regarding claim 1, Lee et al teaches
[claim 1] An integrated circuit (IC) structure, comprising: a semiconductor substrate having a static random-access memory (SRAM) region, an input/output and peripheral (IOP) region, and an edge region spanning tween the SRAM region and the IOP region (figure 1, paragraph 0013, where element 26 is the SRAM region, element 28 is the edge/peripheral region and element 14 is the I/O region where the edge region [element 28] is situated between the SRAM region [element 26] and the I/O region [element 14]),
a shallow trench isolation (STI) structure formed on the semiconductor substrate and defining active regions (figure 2, paragraph 0013, where element 13 is the shallow trench isolation feature and it is formed on the substrate [element 12] and defines an active region [where element 18 is the one time programmable capacitor that is in the same location as the SRAM of figure 1, and is defined by the shallow trench isolation features]),
a SRAM cell formed within the SRAM region (figure 1, paragraph 0013, where element 26 is the SRAM region and an SRAM cell is formed in said region),
the SRAM cell spans a first dimension Ds along the first direction, the edge region spans a second dimension De along the first direction, and a ratio De/Ds equals to 2 or is less than 2 (figure 1, paragraph 0013, where element 26 is the SRAM region and has a dimension DS spanning in the horizontal [x-direction] which is the first direction, and the edge region [element 28] spans a second dimension De in the first direction [x-direction], where the ratio of De/Ds visually is around 2).
However, Lee et al does not specifically disclose
[claim 1] and a backside dielectric layer disposed on a backside of the semiconductor substrate and landing on a bottom surface of the STI structure, wherein the active regions longitudinally are oriented along a first direction, a plurality of gates are formed on the semiconductor substrate and longitudinally oriented along a second direction perpendicular to the first direction, the gates are evenly distributed with a pitch P along the first direction.
However, Liaw does teach
[claim 1] and a backside dielectric layer disposed on a backside of the semiconductor substrate and landing on a bottom surface of the STI structure (figure 3H, paragraph 0031, where element 206 is the STI structure and element 214 is the backside dielectric layer disposed on the substrate),
wherein the active regions longitudinally are oriented along a first direction (figure 3A, paragraph 0034, where element 228 is the active regions and are longitudinally oriented along a first direction [which is the x-direction which maps onto the first direction, x-direction, of Lee et al]),
a plurality of gates is formed on the semiconductor substrate and longitudinally oriented along a second direction perpendicular to the first direction, the gates are evenly distributed with a pitch P along the first direction (figure 3B, paragraph 0034, where element 230 [a and b] is the gate structure longitudinally oriented along a second direction [y-direction] and evenly distributed in the y-direction with a certain pitch, P, which is length 102wp according to paragraph 0055. Where P is being interpreted as "a center to center distance between two gates.” Note: if this is the incorrect interpretation the claim should specify.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee et al in view of Liaw in order to attach a backside dielectric with spaced apart active layers to great an efficient grid structure that is electrically isolated from the rest of the device to maximize efficiency.
Regarding claims 2 and 3,
Lee et al as modified teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose,
[claim 2] The IC structure of claim 1, wherein Ds equals to 2P and De equals to 4P.
[claim 3] The IC structure of claim 1, wherein Ds equals to 2P and De equals to 2P.
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee et al as modified to alter the sizes of each region according to the specific use case and optimization of efficiency of each particular region.
Regarding claim 5, 6
Lee et al as modified teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 5] The IC structure of claim 1, wherein the SRAM cell includes two inverters cross-coupled and includes a field-effect transistors (FET); each of the active regions includes multiple channel layers vertically stacked and spaced away from each other; and the FET includes a source, a drain, a gate interposed between the source and drain, wherein the gate is further extending to wrap around each of the multiple channel layers.
[claim 6] The IC structure of claim 5, wherein one of the source and the drain further includes a dielectric material layer embedded in an epitaxial semiconductor feature.
However, Liaw teaches
[claim 5] The IC structure of claim 1, wherein the SRAM cell includes two inverters cross-coupled and includes a field-effect transistors (FET) (figure 2B, paragraph 0024, where elements 110 and 112 are two inverters cross-coupled with field effect transistors [114, 118, 122, 124]);
each of the active regions includes multiple channel layers vertically stacked and spaced away from each other; and the FET includes a source, a drain, a gate interposed between the source and drain, wherein the gate is further extending to wrap around each of the multiple channel layers (figures 3I-3L, paragraphs 0033-0035 where the active layers [element 228] are stacked vertically upon one another and separated from one another, and each FET includes a source [element 122S/124S] and drain [elements 126D] and a gate [element 232] which is interposed between the source/drain and the active layer [gate surrounds active layer and thus wraps around the active layer]).
[claim 6] The IC structure of claim 5, wherein one of the source and the drain further includes a dielectric material layer embedded in an epitaxial semiconductor feature (figure 3H , paragraph 0048, where element 208 is the dielectric material embedded in the layer that contains the source/drain epitaxial material).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee et al as modified to incorporate the teachings of Liaw to incorporate a source drain material with dielectric properties surrounding it to electrically isolate the conductive material to allow for greater performance of the device.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20220344358), Liaw (US 20220336474) and in further view of Liaw (US 20200135741).
Lee et al as modified teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 4] The IC structure of claim 1, wherein the bottom surface of the STI structure and a bottom surface of the semiconductor substrate are coplanar.
However, Liaw teaches
[claim 4] The IC structure of claim 1, wherein the bottom surface of the STI structure and a bottom surface of the semiconductor substrate are coplanar (figure 14, paragraph 0027, where element 404 is the STI [isolation trench] and element 402 is the substrate where the bottom surface of each is coplanar with one another).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee et al as modified to incorporate the teachings of Liaw in order to make the trench and substrate bottoms coplanar to maximize efficiency of material used, keeping electrical properties in tact while also minimizing the amount of material used.
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20220344358), Liaw (US 20220336474) and in further view of Liaw (US 20230012680).
Lee et al as modified teaches all of the limitations of the parent claim, claim 5, but does not specifically disclose,
[claim 7] The IC structure of claim 5, further comprising a backside via formed on the backside of the semiconductor substrate and landing on one of the source and the drain, wherein the backside via is partially embedded in the semiconductor substrate; and the backside via includes a conductive plug with a dielectric layer surrounding a sidewall of the conductive plug and separating the conductive plug from the semiconductor substrate.
[claim 8] The IC structure of claim 7, wherein a bottom surface of the backside via is coplanar with a bottom surface of the backside dielectric layer.
However, Liaw does teach
[claim 7] The IC structure of claim 5, further comprising a backside via formed on the backside of the semiconductor substrate and landing on one of the source and the drain, wherein the backside via is partially embedded in the semiconductor substrate (figure 3L, paragraphs 0024, and 0037 where elements 122s and 140.sub.2 [151] contain the backside via which contacts the source [element 122s] and is partially embedded in the semiconductor substrate [element 216 is in place of element 220 of Lee et al which is the substrate]);
and the backside via includes a conductive plug with a dielectric layer surrounding a sidewall of the conductive plug and separating the conductive plug from the semiconductor substrate (figure 3L, paragraph 0037, where element 122s is the backside conductive plug which is surrounded by a dielectric layer [element 214] and is separated from the substrate [element 216 in place of the substrate from Lee et al]).
[claim 8] The IC structure of claim 7, wherein a bottom surface of the backside via is coplanar with a bottom surface of the backside dielectric layer (figure 3L, paragraph 0037, where element 122s is coplanar with the backside dielectric layer [element 214]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Lee et al as modified to incorporate the teachings of Liaw in order to contact the source/drain from a backside to form more connection points for greater control of the semiconductor device.
Claim(s) 10-12 and 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukano (US 20080304313) in view of Horch (US 6790713).
Fukano teaches
[claim 10] An integrated circuit structure, comprising: a semiconductor substrate having a static random-access memory (SRAM) region, an input/output and peripheral (IOP) region, and an edge region spanning tween the SRAM region and the IOP region (figure 1, paragraph 0031, where the cell array [element 1] is the SRAM, element 2 [LS/A] is the edge region and spans between the SRAM region [cell array] and the I/O region [element 3], all situated on a substrate);
a n-type doped well continuously extending through the SRAM region and the edge region along a first direction; a p-type doped well continuously extending through the SRAM region and the edge region along the first direction (figure 2, paragraph 0032, where element 1 [cell array] is part of the SRAM region, and element LS/A is the peripheral/edge region, where an n-type doped well and p-type doped well continuously extend through the SRAM region and the edge region in the first direction [y-direction]);
a plurality of gates longitudinally oriented along a second direction perpendicular to the first direction, wherein the gates are evenly distributed in the SRAM region and the edge region with a periodic pitch P (figure 10, paragraph 0050, where the gate electrodes [as shown in figure 10 with no element number] are distributed in the SRAM region and the peripheral region [element LS/A] at a certain pitch [regular intervals] in the second direction [x-direction]. Where P is being interpreted as "a center to center distance between two gates.” Note: if this is the incorrect interpretation the claim should specify.).
wherein the SRAM region includes SRAM cells each spanning a first dimension Ds along the first direction, the edge region spans a second dimension De along the first direction, and a ratio De/Ds equals to 2 or is less than 2 (figure 10, paragraph 0050, where the SRAM region is the cell array region and spans a first direction [y-direction] with a length Ds, and the edge region [LS/A region] spans a second dimension De in the y-direction, where De/Ds is equal to 2 or less than 2 [visually closer to 1]).
[claim 21] An integrated circuit structure, comprising: a semiconductor substrate having a static random-access memory (SRAM) region, an input/output and peripheral (IOP) region, and an edge region spanning tween the SRAM region and the IOP region (figure 1, paragraph 0031, where the cell array [element 1] is the SRAM, element 2 [LS/A] is the edge region and spans between the SRAM region [cell array] and the I/O region [element 3], all situated on a substrate);;
a n-type doped well continuously extending through the SRAM region and the edge region along a first direction; a p-type doped well continuously extending through the SRAM region and the edge region along the first direction (figure 2, paragraph 0032, where element 1 [cell array] is part of the SRAM region, and element LS/A is the peripheral/edge region, where an n-type doped well and p-type doped well continuously extend through the SRAM region and the edge region in the first direction [y-direction]);
a plurality of gates longitudinally oriented along a second direction perpendicular to the first direction, wherein the gates are evenly distributed in the SRAM region and the edge region with a periodic pitch P (figure 10, paragraph 0050, where the gate electrodes [as shown in figure 10 with no element number] are distributed in the SRAM region and the peripheral region [element LS/A] at a certain pitch [regular intervals] in the second direction [x-direction]);
wherein the SRAM region includes SRAM cells each spanning a first dimension Ds along the first direction, the edge region spans a second dimension De along the first direction, a ratio De/Ds equals to 2 or is less than 2 (figure 10, paragraph 0050, where the SRAM region is the cell array region and spans a first direction [y-direction] with a length Ds, and the edge region [LS/A region] spans a second dimension De in the y-direction, where De/Ds is equal to 2 or less than 2 [visually closer to 1]).
the first active region spans a first width W1 along the second direction, the second and third active regions span a second width W2 along the second direction, and the second and third active regions are aligned along the first direction. (figure 10, paragraph 0050, where the first active region is defined by the top left-hand corner gate electrode in the cell:array and spans a first width, W1, in the second direction [x-direction], the second active region is the gate electrode in the n-well in the cell:array region just below the first active region in the y-direction, and third active region [located directly below the second] is located in the edge-region [LS/A] and in the n-well, and each spans a second width, W2, where they are aligned in a first direction [y-direction]).
However, Fukano does not specifically disclose
[claim 10] a shallow trench isolation (STI) structure formed on the semiconductor substrate and defined a first, second and third active regions longitudinally oriented along the first direction;
and a backside dielectric layer contacting a bottom surface of the semiconductor substrate and a bottom surface of the STI structure,
[claim 21] a shallow trench isolation (STI) structure formed on the semiconductor substrate and defined a first, second and third active regions longitudinally oriented along the first direction;
and a backside dielectric layer contacting a bottom surface of the semiconductor substrate and a bottom surface of the STI structure,
W1 being greater than W2,
However, Horch does teach
[claim 10] a shallow trench isolation (STI) structure formed on the semiconductor substrate and defined a first, second and third active regions longitudinally oriented along the first direction (figure 12, col 9 lines 38-52, where STI separates the three active regions [1430, 1432, 1434] oriented in the first direction [y-direction] in a longitudinal manner),
and a backside dielectric layer contacting the semiconductor substrate and a bottom surface of the STI structure (figure 10A, col 8 lines 25-48, where element 732 is the backside dielectric contacting a bottom portion of the STI and contacting the bottom surface of the substrate when put in the place of the STI of Fukano, where element 220 of Fukano is the substrate directly below the STI).
[claim 21] a shallow trench isolation (STI) structure formed on the semiconductor substrate and defined a first, second and third active regions longitudinally oriented along the first direction (figure 12, col 9 lines 38-52, where STI separates the three active regions [1430, 1432, 1434] oriented in the first direction [y-direction] in a longitudinal manner);
and a backside dielectric layer contacting the semiconductor substrate and a bottom surface of the STI structure (figure 10A, col 8 lines 25-48, where element 732 is the backside dielectric contacting a bottom portion of the STI and contacting the bottom surface of the substrate when put in the place of the STI of Fukano, where element 220 of Fukano is the substrate directly below the STI),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Fukano to incorporate the teachings of Horsh to put a dielectric layer below the shallow trench isolation region to better control the resistance of each active region.
However, Fukano as modified does not specifically disclose
[claim 10] [a backside dielectric contacting] a bottom surface of the semiconductor substrate.
[claim 21] [a backside dielectric contacting] a bottom surface of the semiconductor substrate, W1 being greater than W2,
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Fukano as modified to change the length of the backside dielectric layer to contact the bottom surface of the substrate if such amount of electrical isolation is needed for each active regions to maximize the efficiency of the device. Additionally, it would have been obvious to alter the dimension of W1 and W2 to maximize efficiency of the device by optimizing the size of each active region for specific use cases.
Regarding claims 11, 22
Fukano further teaches,
[claim 11] The IC structure of claim 10, wherein the first active region formed in the p-type doped well and continuously extending from the SRAM region to the edge region; the second active region formed in the n-type doped well and disposed within the SRAM region; and the third active region formed in the n-type doped well and disposed within the edge region (figure 10, paragraph 0050, where the first active region is defined by the top left-hand corner gate electrode in the cell:array and spans a first width, W1, in the second direction [x-direction], the second active region is the gate electrode in the n-well in the cell:array region just below the first active region in the y-direction, and third active region [located directly below the second] is located in the edge-region [LS/A] and in the n-well, and each spans a second width, W2, where they are aligned in a first direction [y-direction]).
[claim 22] The IC structure of claim 21, wherein the first active region formed in the p-type doped well and continuously extending from the SRAM region to the edge region; the second active region formed in the n-type doped well and disposed within the SRAM region; and the third active region formed in the n-type doped well and disposed within the edge region (figure 10, paragraph 0050, where the first active region is defined by the top left-hand corner gate electrode in the cell:array and spans a first width, W1, in the second direction [x-direction], the second active region is the gate electrode in the n-well in the cell:array region just below the first active region in the y-direction, and third active region [located directly below the second] is located in the edge-region [LS/A] and in the n-well, and each spans a second width, W2, where they are aligned in a first direction [y-direction]).
Regarding claim 12,
Fukano as modified teaches all of the limitations of the parent claim, claim 11, and Fukano additionally discloses
12. (Original) The IC structure of claim 11, wherein the first active region spans a first width W1 along the second direction; the second and third active regions span a second width W2 along the second direction, and the second and third active regions are aligned along the first direction (figure 10, paragraph 0050, where the first active region is defined by the top left-hand corner gate electrode in the cell:array and spans a first width, W1, in the second direction [x-direction], the second active region is the gate electrode in the n-well in the cell:array region just below the first active region in the y-direction, and third active region [located directly below the second] is located in the edge-region [LS/A] and in the n-well, and each spans a second width, W2, where they are aligned in a first direction [y-direction]).
However Fukano as modified does not specifically disclose
[claim 12] W1 being greater than W2.
However, according to MPEP 2144.04 CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Fukano as modified to alter the dimension of W1 and W2 to maximize efficiency of the device by optimizing the size of each active region for specific use cases.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukano (US 20080304313), Horch (US 6790713) and in further view of Liaw (US 20200135741).
Fukano as modified teaches all of the limitations of the parent claim, claim 10, but does not specifically disclose
[claim 16] The IC structure of claim 10, wherein Ds equals to 2P and De equals to 4P; and the bottom surface of the STI structure and the bottom surface of the semiconductor substrate are coplanar.
However, Liaw does teach
[claim 16] the bottom surface of the STI structure and the bottom surface of the semiconductor substrate are coplanar (figure 14, paragraph 0027, where element 404 is the STI [isolation trench] and element 402 is the substrate where the bottom surface of each is coplanar with one another).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Fukano as modified to incorporate the teachings of Liaw in order to make the trench and substrate bottoms coplanar to maximize efficiency of material used, keeping electrical properties in tact while also minimizing the amount of material used.
However, Fukano as modified does not specifically disclose
[claim 16] The IC structure of claim 10, wherein Ds equals to 2P and De equals to 4P;
However, according to MPEP 2144.04 IV. CHANGES IN SIZE, SHAPE, OR SEQUENCE OF ADDING INGREDIENTS
A. Changes in Size/Proportion
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Fukano as modified to modify the sizes of the SRAM and Edge region to match integer intervals of the pitch of the gate electrodes to optimize the specific device for use.
Claim(s) 13 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Fukano (US 20080304313), Horch (US 6790713) and in further view of Su et al (US 20220352256).
Fukano as modified teaches all of the limitations of the parent claims, claims 11 and 21, but does not specifically disclose
[claim 13] The IC structure of claim 11, further comprising a first source/drain (S/D) feature formed on the first active region; a second S/D feature formed on the second active region; a first backside via contacting a bottom surface of the first S/D feature; and a second backside via contacting a bottom surface of the second S/D feature.
[claim 23] The IC structure of claim 21, further comprising a first source/drain (S/D) feature formed on the first active region; a second S/D feature formed on the second active region; a first backside via contacting a bottom surface of the first S/D feature; and a second backside via contacting a bottom surface of the second S/D feature.
However, Su et al does teach
[claim 13] The IC structure of claim 11, further comprising a first source/drain (S/D) feature formed on the first active region; a second S/D feature formed on the second active region; a first backside via contacting a bottom surface of the first S/D feature; and a second backside via contacting a bottom surface of the second S/D feature (figures 3, paragraph 0018, where elements 232S1 and 232S2 are the first and second backside vias contacting a first surface of the first and second /D feature).
[claim 23] The IC structure of claim 21, further comprising a first source/drain (S/D) feature formed on the first active region; a second S/D feature formed on the second active region; a first backside via contacting a bottom surface of the first S/D feature; and a second backside via contacting a bottom surface of the second S/D feature (figures 3, paragraph 0018, where elements 232S1 and 232S2 are the first and second backside vias contacting a first surface of the first and second /D feature).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Fukano as modified to incorporate the teachings of Su et al in order to contact the source/drain features with conductive material to functionally allow the source/drain to function properly in making a memory device.
Allowable Subject Matter
Claims 9, 14, 15 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Pao et al (US 20190096474), Li et al (US 20190088660), Liaw (US 20150243667) as memory devices with similar structures of edge regions with SRAM core regions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 572-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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