DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Group II, claims 11-17, in the reply filed on 8 June 2026 is acknowledged. Claims 1-10 and 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. The restriction requirement – between process of making and product made – is deemed proper and made final.
Applicants’ arguments, see page 8, filed 8 June 2026, with respect to the Election of Species Requirement have been fully considered and are persuasive. The Election of Species Requirement has been withdrawn.
Response to Amendment
The Office acknowledges receipt on 8 June 2026 of Applicants’ amendments in which claims 1-10 and 18-20 are cancelled and claims 21-33 are newly added.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-33 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21, lines 1-3, recites “a method, comprising: a substrate including a semiconductor layer; a transistor on the substrate and including,” which is indefinite because it is unclear how a method comprises a substrate, semiconductor layer, and transistor.” For the purpose of compact prosecution and to better comport with the remainder of the claim, this will be interpreted as “a method of forming a transistor, the method comprising.” Claims 22-30 are rejected due to their dependence from base claim 21.
Claim 21, line 12, recites “a second source/drain region,” which is indefinite because it is unclear whether this refers to the “second source/drain region” recited in the previous lines. For the purpose of compact prosecution and to better comport with the remainder of the claim, this will be interpreted as “the second source/drain region.” Claims 22-30 are rejected due to their dependence from base claim 21.
Claim 31, line 6, recites “the source/drain contact,” which is indefinite because it lacks a proper antecedent basis. For the purpose of compact prosecution and to better comport with the remainder of the claim, this will be interpreted as “the backside source/drain contact.” Claims 32-33 are rejected due to their dependence from base claim 31.
Claim 32, lines 2 and 3, recites “the bottom isolation layer,” which is indefinite because it lacks a proper antecedent basis. For the purpose of compact prosecution and to better comport with the remainder of the claim, this will be interpreted as “a bottom isolation layer.”
Claim 32, line 5, recites “a bottom isolation layer,” which is indefinite because it is unclear whether this is the same “bottom isolation layer” recited previously in the claim. For the purpose of compact prosecution and to better comport with the remainder of the claim, this will be interpreted as “the bottom isolation layer.” Claim 33 is rejected due to its dependence from intermediate claim 32.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11, 12, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US20230061857A1) in view of Xie et al. (US20230178433A1).
Regarding claim 11, Lin teaches a method, comprising:
forming a plurality of stacked channels (208) of a transistor (transistor of 200) above a semiconductor layer (202) of a substrate (202) {Fig. 2; [0014]};
forming a first trench (2220) in the semiconductor layer (202) {Fig. 4; [0020]};
forming a first bottom semiconductor structure (224) in the first trench (2220) and having a top surface lower than a lowest channel (208) of the transistor (transistor of 200) {Fig. 5; [0021]};
forming a first bottom isolation layer (228) on the top surface of the bottom semiconductor structure (224) {Fig. 7; [0024]};
forming a first source/drain region (226) of the transistor (transistor of 200) on the first bottom isolation layer (228) {Fig. 7; [0024]};
forming a backside trench (trench removing 224) exposing the first source/drain region (226) by selectively etching the first bottom semiconductor structure (224) {Fig. 14; [0038]}; and
forming a backside source/drain contact (280) in the backside trench (trench removing 224) electrically coupled to the first source/drain region (226) {Fig. 14; [0038]}.
Lin does not teach forming a backside trench in the substrate by selectively etching the first bottom semiconductor structure with respect to the semiconductor layer.
In an analogous art, Xie teaches in Figs. 10 and 11 and paragraph [0035, 0049, 0067] forming a backside trench (64) in a substrate (10) by selectively etching the first bottom semiconductor structure (40) with respect to the semiconductor layer (10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s method based on the teachings of Xie – to form a backside trench in the substrate by selectively etching the first bottom semiconductor structure with respect to the semiconductor layer – because applying a known technique (e.g., as taught by Xie) in the same way to enhance another known technique (e.g., as taught by Lin) to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C).
Regarding claim 12, Lin as modified by Xie teaches the method of claim 11, and Lin further teaches comprising forming a frontside source/drain contact (260) above and electrically coupled to the first source/drain region (226) {Fig. 11; [0032]}.
Regarding claim 17, Lin as modified by Xie teaches the method of claim 16, and Lin further teaches comprising forming a silicide (262) between the first source/drain region (226) and the backside source/drain contact (280) {Fig. 15; [0033], along a diagonal line drawn to pass through 280 and 226}.
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Xie as applied to claim 11 above, and further in view of Wang et al. (DE102021102235A1), using Wang et al. (US20230253313A1) as the English translation.
Regarding claim 13, Lin as modified by Xie teaches the method of claim 11, and Lin further teaches comprising
forming inner spacers (218) between the stacked channels (208) {Fig. 3; [0019]}.
Lin does not teach forming the first trench includes: etching the semiconductor layer with a first etching process before forming the inner spacers; and deepening the first trench by etching the semiconductor layer with a second etching process after forming the inner spacers.
In an analogous art, Wang teaches in Figs. 5B, 6B, 7B, and 8 and paragraphs [0046, 0048, 0050] forming a first trench (R1 and/or R3) includes: etching {Figs. 5B, 6B} a semiconductor layer (112) with a first etching process (etch to create R1) before forming {Fig. 7B} inner spacers (170); and deepening {Fig. 8} the first trench (R1 and/or R3) by etching the semiconductor layer (112) with a second etching process after forming the inner spacers (170). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s method as modified by Xie based on the teachings of Wang – to form the first trench by: etching the semiconductor layer with a first etching process before forming the inner spacers; and deepening the first trench by etching the semiconductor layer with a second etching process after forming the inner spacers – because applying a known technique (e.g., as taught by Wang) in the same way to enhance another known technique (e.g., as taught by Lin and Xie) to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C).
Regarding claim 14, Lin as modified by Xie and Wang teaches the method of claim 13, but Lin does not teach wherein a sidewall of the first trench has a step after the second etching process.
However, the instant application discloses in paragraph [00082] that a step is inherently created by the application of multiple source/drain etching processes. Wang teaches multiple source drain etching processes. Accordingly, Wang implicitly teaches a sidewall of the first trench has a step after the second etching process. The motivation for this modification is identified with respect to intermediate claim 13.
Furthermore, Wang teaches in Fig. 8 a step in the trench (R1 and R3) that is formed by the upper surface of gate sidewall spacer (162). The motivation for this modification is identified with respect to intermediate claim 13.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Xie as applied to claim 11 above, and further in view of Zou et al. (US20240420990A1).
Regarding claim 15, Lin as modified by Xie teaches the method of claim 11, but Lin does not teach comprising:
forming a second trench in the semiconductor layer;
forming a second bottom semiconductor structure in the second trench and having a top surface lower than the lowest channel of the first transistor;
forming a second bottom isolation layer on the top surface of the bottom semiconductor structure; and
forming a second source/drain region of the transistor on the second bottom isolation layer.
Zou teaches in Fig. 3A and paragraph [0076]: forming a second trench (left/right most trench filled with 202) in a semiconductor layer (106); forming a second bottom semiconductor structure (left/right most 202) in the second trench (left/right most trench filled with 202) and having a top surface lower than a lowest channel (112) of a first transistor (transistor of 100); forming a second bottom isolation layer (left/right most 108) on the top surface of the bottom semiconductor structure (left/right most 202); and forming a second source/drain region (left/right most 208) of the transistor (transistor of 100) on the second bottom isolation layer (left/right most 108). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s method as modified by Xie based on the teachings of Zou, as identified above, because applying a known technique (e.g., as taught by Zou) in the same way to enhance another known technique (e.g., as taught by Lin and Xie) to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C). Moreover, Zou’s operations reduce resources (e.g., manufacturing operations, materials, manufacturing time, etc.) for manufacturing a transistor by eliminating differences in forming the source/drain regions on opposite sides of a channel stack.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Xie as applied to claim 11 above, and further in view of Xie et al. (US20230139929A1) and Yen et al. (US20230009820A1).
Regarding claim 16, Lin as modified by Xie teaches the method of claim 11, but Lin does not teach comprising:
forming a lower trench isolation subregion of a trench isolation region;
forming a dielectric layer of a same material as the first bottom isolation layer on the lower trench isolation subregion; and
forming an upper trench isolation subregion of the trench isolation region directly above the lower trench isolation subregion and separated from the lower trench isolation subregion by the dielectric layer.
In an analogous art, Xie ‘929 teaches in Fig. 15A:
forming a lower trench isolation subregion (42) of a trench isolation region (region of 12, 28, 42) {[0074]};
forming a dielectric layer (28) on the lower trench isolation subregion (42) {[0074]}; and
forming an upper trench isolation subregion (12) of the trench isolation region (region of 12, 28, 42) directly above the lower trench isolation subregion (42) and separated from the lower trench isolation subregion (42) by the dielectric layer (28) {[0032]}.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s method as modified by Xie based on the teachings of Xie ‘929, as identified above, because applying a known technique (e.g., as taught by Xie ‘929) in the same way to enhance another known technique (e.g., as taught by Lin and Xie) to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C).
Lin does not teach the dielectric layer of a same material as the first bottom isolation layer.
However, Xie ‘929 teaches in paragraph [0049] the dielectric layer may be silicon nitride.
Yen teaches a first bottom isolation layer (109B) made of silicon nitride disposed on a semiconductor structure (106) and having a source/drain region (110) disposed thereon. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s method as modified by Xie and Xie ‘929 based on the teachings of Yen – such that the dielectric layer is formed of a same material as the first bottom isolation layer – because all the claimed elements (e.g., dielectric layer, first bottom isolation layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yen) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 21-23 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Zou.
Regarding claim 21, as interpreted in view of the indefiniteness rejection, Lin teaches a method of forming a transistor, the method comprising:
forming a bottom semiconductor structure (224) in a substrate (202), the substrate (202) including a semiconductor layer (202), wherein the bottom semiconductor structure (224) is in contact with a sidewall of the semiconductor layer (202) and has a different semiconductor material (SiGe) than the semiconductor layer (202, Si/Ge/SiC/SiGe) {Fig. 5; [0021]};
forming a first source/drain region (226), wherein the transistor (transistor of 200) includes a second source/drain region (232) and a plurality of stacked channels (208 and/or 2080) extending between the first source/drain region (226) and the second source/drain region (232) {Fig. 13; [0026]}; and
forming a backside source/drain contact (280) in the substrate (202) directly below and electrically coupled to the second source/drain region (280) {Fig. 14; [0038], orientation of Fig. 14 may be rotated to match recited orientation}.
Lin does not teach forming a bottom isolation layer above and in contact with the bottom semiconductor structure; the first source/drain region being above and in contact with the bottom isolation structure.
Zou teaches in Fig. 3A forming a bottom isolation layer (108) above and in contact with a bottom semiconductor structure (202); a first source/drain region (208) being above and in contact with the bottom isolation structure (202). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s method based on the teachings of Zou – to form a bottom isolation layer above and in contact with the bottom semiconductor structure; the first source/drain region being above and in contact with the bottom isolation structure – because applying a known technique (e.g., as taught by Zou) in the same way to enhance another known technique (e.g., as taught by Lin) to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C).
Regarding claim 22, Lin as modified by Zou teaches the method of claim 21, and Lin further teaches wherein the bottom semiconductor structure (224) and the channels (208 and/or 2080) include silicon, wherein the bottom semiconductor structure includes (224) silicon germanium {[0014, 0021]}.
Regarding claim 23, Lin as modified by Zou teaches the method of claim 21, and Lin further teaches comprising forming a frontside source/drain contact (306) directly above and electrically coupled to the second source/drain region (232) {Fig. 16; [0041]}.
Regarding claim 28, Lin as modified by Zou teaches the method of claim 21, and Lin further teaches wherein the semiconductor layer (202) is silicon and the bottom semiconductor structure (224) is silicon germanium {[0014, 0021]}.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Zou as applied to claim 21 above, and further in view of Wang.
Regarding claim 24, Lin as modified by Zou teaches the method of claim 21, but Lin does not teach wherein the sidewall of the semiconductor layer has a step that is in contact with the bottom semiconductor structure.
However, the instant application discloses in paragraph [00082] that a step is inherently created by the application of multiple source/drain etching processes. Wang teaches multiple source drain etching processes to form a trench by: etching a semiconductor layer with a first etching process before forming inner spacers; and deepening the trench by etching the semiconductor layer with a second etching process after forming the inner spacers. Accordingly, Wang implicitly teaches a sidewall of the first trench has a step after the second etching process. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s method as modified by Zou based on the teachings of Wang – so the sidewall of the semiconductor layer has a step that is in contact with the bottom semiconductor structure – because applying a known technique (e.g., as taught by Wang) in the same way to enhance another known technique (e.g., as taught by Lin and Zou) to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C).
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Zou as applied to claim 21 above, and further in view of Lin et al (US20220165848A1).
Regarding claim 29, Lin as modified by Zou teaches the method of claim 21, and Lin further teaches wherein the bottom semiconductor structure (224) has a concave top surface {Fig. 5}.
Lin does not teach the bottom isolation layer has a convex bottom surface in contact with the concave top surface of the bottom semiconductor structure.
Lin ‘848 teaches in Fig. 11 and paragraphs [0021, 0029] a bottom isolation layer (246) has a convex bottom surface in contact with the concave top surface of a bottom semiconductor structure (226B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s method as modified by Zou based on the teachings of Lin ‘848, as identified above, because all the claimed elements (e.g., bottom isolation layer, bottom semiconductor structure) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Lin ‘848) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Zou and Lin ‘848 as applied to claim 29 above, and further in view of Yen.
Regarding claim 30, Lin as modified by Zou and Lin ‘848 teaches the method of claim 29, but Lin does not teach wherein the first source/drain region has a convex bottom surface in contact with the bottom isolation layer.
In an analogous art, Yen teaches in Fig. 13 a source/drain region (110) has a convex bottom surface in contact with a bottom isolation layer (109B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s method as modified by Zou and Lin ‘848 based on the teachings of Yen, as identified above, because all the claimed elements (e.g., source/drain region, bottom isolation layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Yen) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 31 and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Wang.
Regarding claim 31, as interpreted in view of the indefiniteness rejection, Lin teaches a method, comprising:
forming a substrate (202) including a semiconductor layer (202) {Fig. 2; [0014]};
forming a plurality of stacked channels (208 and/or 2080) of a transistor (transistor of 200) above the semiconductor layer (202) {Fig. 2; [0014]};
a first source/drain region (226) in contact with the channels (208 and/or 2080) {Fig. 7; [0024]};
forming a backside source/drain contact (280) in the substrate (202) directly below and electrically coupled to the first source/drain region (226) {Fig. 14; [0038]}; and
forming a frontside source/drain contact (260) directly above and electrically coupled to the first source/drain region (226) {Fig. 11; [0032]}.
Lin does not teach a sidewall of the backside source/drain contact has a step in contact with a step in a sidewall of the semiconductor layer.
However, the instant application discloses in paragraph [00082] that a step is inherently created by the application of multiple source/drain etching processes. Wang teaches multiple source drain etching processes to form a trench by: etching a semiconductor layer with a first etching process before forming inner spacers; and deepening the trench by etching the semiconductor layer with a second etching process after forming the inner spacers. Accordingly, Wang implicitly teaches a sidewall of the first trench has a step after the second etching process. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lin’s method based on the teachings of Wang – so a sidewall of the source/drain contact has a step in contact with a step in a sidewall of the semiconductor layer – because applying a known technique (e.g., as taught by Wang) in the same way to enhance another known technique (e.g., as taught by Lin and Zou) to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C).
A consequence of this modification is that Lin’s backside source/drain contact (280), which fills the space previously created by the formation of Lin’s trench (as modified by Wang’s multi-etching process) will have a sidewall step in contact with a step in a sidewall of Lin’s semiconductor layer (202).
Regarding claim 32, as interpreted in view of the indefiniteness rejection, Lin as modified by Wang teaches the method of claim 31, and Lin further teaches further comprising:
forming a bottom semiconductor structure (224) below and in contact with a bottom isolation layer (228) and in contact with the semiconductor layer (202), the bottom semiconductor structure (224) having a different semiconductor material (SiGe) than the semiconductor layer (202, Si/Ge/SiC/SiGe) {Fig. 5; [0021]};
forming the bottom isolation layer (228) above and in contact with the bottom semiconductor structure (224) {Fig. 7; [0024]}; and
forming a second source/drain region (232) of the transistor (transistor of 200) in contact with the channels (208 and/or 2080) {Fig. 13; [0026]}.
Allowable Subject Matter
Claims 25-27 and 33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 25, the prior art does not teach, suggest or motivate one having ordinary skill in the art to have the recited subject matter of “a trench isolation region including: a lower trench isolation subregion in contact with the bottom semiconductor structure and the semiconductor layer; and an upper trench isolation subregion above the lower trench isolation subregion and separated from the lower trench isolation subregion by a dielectric layer of a same material as the bottom isolation layer” in combination with the other limitations of the claim. Claims 26 and 27 are allowable due to their dependence from intermediate claim 25.
Regarding claim 33, the prior art does not teach, suggest or motivate one having ordinary skill in the art to have the recited subject matter of “a trench isolation region including: a lower trench isolation subregion in contact with the bottom semiconductor structure and the semiconductor layer; and an upper trench isolation subregion above the lower trench isolation subregion and separated from the lower trench isolation subregion by a dielectric layer of a same material as the bottom isolation layer” in combination with the other limitations of the claim.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. (US20220352074A1) teaches an integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit. But Chen does not teach the above-identified subject matter of allowable claims 25-27 and 33.
Conclusion
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/D.W.W./ Examiner, Art Unit 2891
/MATTHEW C LANDAU/ Supervisory Patent Examiner, Art Unit 2891
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