DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-13 and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al (CN 110863240), an English computer translation (CT) is provided, in view of Hourai et al (US 6,245,430).
Wei et al teaches a method for producing single crystal silicon wafers for insulated gate bipolar transistors (IGBT) (CT [0002], [0019], [0080]), the method comprising: producing a single crystal silicon ingot, the single crystal silicon ingot having a profile of a ratio between (i) a growth velocity, v, and (ii) an axial temperature gradient, G, the single crystal silicon ingot being produced by: determining a v/G profile of the single crystal silicon ingot (Fig 4 shows ratio of V/G); selecting an ingot nitrogen concentration at which the ingot is free of gate oxide integrity failures across the ingot radius based on the radial v/G profile of the ingot (Fig 4; CT [0023]-[0080] teaches a nitrogen concentration of 1x1014 to 5x1015 atoms/cm3; nitrogen is doped to expand the pull out speed tolerance for growing defect-free crystals without COP; and the types and distribution of defects depend on the ratio of V/G of the pulling speed to the temperature gradient along the crystal growth direction; and Fig 4 shows V/G values for producing a Pv, defect-free, region across the entire radius of the crystal); adding polycrystalline silicon to a crucible disposed within a growth chamber of an ingot puller apparatus; heating the polycrystalline silicon to cause a silicon melt to form in the crucible (CT [0083] teaches polycrystalline Si raw material is melted in a crucible to generate a melt); adding nitrogen to the silicon melt to achieve the selected ingot nitrogen concentration (CT [0083] teaches adding silicon wafer with nitride films to adjust the nitrogen doping amount to reach 1x1014 atoms/cm3); and pulling a single crystal silicon ingot doped with nitrogen from the melt; and slicing a plurality of wafers from the single crystal silicon ingot, each wafer of the plurality of wafers having an oxygen concentration of less than 2.75×10.sup.17 atoms/cm3 (CT [0080]-[0090] teaches an oxygen concentration of 1x1017 to 4x1017 atoms/cm3). Overlapping ranges are prima facie obvious (MPEP 2144.05). Wei et al teaches the being free of crystal originated particles and being free of gate-oxide integrity failures (CT [0023] teaches growing defect-free crystals without COP, dislocation clusters and OSF cores).
Wei et al teaches controlling the V/G ratio to produce defect-free wafers. Wei et al does not explicitly teach the single crystal silicon ingot having a radial profile of a ratio between (i) a growth velocity, v, and (ii) an axial temperature gradient, G, the single crystal silicon ingot being produced by: determining a radial v/G profile of the single crystal silicon ingot.
Hourai et al teaches a Czochralski crystal growth method comprising careful control of the pulling rate V and the temperature gradient G permits crystals to be formed that are free from OSF rings, and other types of defects; and a constant V/G values in the radial direction from the crystal center all the way to its periphery permits crystals to form in the no-fault region, throughout the entire radial direction of the crystal (Abstract; Fig 2-5; col 7, ln 1 to col 8, ln 35), which clearly suggests a radial profile of a ratio between (i) a growth velocity, v, and (ii) an axial temperature gradient, G, the single crystal silicon ingot being produced by: determining a radial v/G profile of the single crystal silicon ingot.
Referring to claim 2, the combination of Wei et al and Hourai et al teaches doping nitrogen into a silicon single crystal ingot; and controlling the V/G from the center to all the way to its periphery to form in no-fault region to form defect-free crystals. The combination of Wei et al and Hourai et al teaches determining a difference between the ratio of v/G at the center of the ingot and the ratio of v/G at a point halfway between the center and a circumferential edge of the ingot (Hourai teaches determining the V/G from the center to the periphery which would include a halfway point in Figs 2-5 and having a constant V/G); and selecting a nitrogen concentration at which the ingot is free of gate oxide integrity failures across the ingot radius based on the determined difference between the ratio of v/G at the center of the ingot and the ratio of v/G at a point halfway between the center and a circumferential edge of the ingot (Wei CT [0023]-[0080] teaches a nitrogen concentration of 1x1014 to 5x1015 atoms/cm3; nitrogen is doped to expand the pull out speed tolerance for growing defect-free crystals without COP; and the types and distribution of defects depend on the ratio of V/G of the pulling speed to the temperature gradient along the crystal growth direction; and Fig 4 shows V/G values for producing a Pv, defect-free, region across the entire radius of the crystal).
Referring to claim 3, the combination of Wei et al and Hourai et al teaches the nitrogen concentration at which the ingot is free of gate oxide integrity failures across the ingot radius is determined based on a ratio between the ratio of v/G at the center of the ingot and the ratio of v/G at a point halfway between the center and a circumferential edge of the ingot. (Wei CT [0023]-[0080] teaches a nitrogen concentration of 1x1014 to 5x1015 atoms/cm3; nitrogen is doped to expand the pull out speed tolerance for growing defect-free crystals without COP; and the types and distribution of defects depend on the ratio of V/G of the pulling speed to the temperature gradient along the crystal growth direction; and Fig 4 shows V/G values for producing a Pv, defect-free, region across the entire radius of the crystal; and Hourai teaches a constant V/G from the center to the periphery to produce defect-free crystals which would clearly suggests a ratio of 1 for the center and a point halfway from the center and an edge).
Referring to claim 4, the combination of Wei et al and Hourai et al teaches pulling test ingot and evaluating V/G and defects (Hourai Fig 2-5; Wei Fig 4), which clearly suggests the radial v/G profile is determined empirically by a ramping test method comprising: pulling a test ingot in the ingot puller apparatus, the test ingot being grown while ramping the growth velocity; determining the growth velocity, v, at a given radial position of the test ingot at a transition from interstitial-defects; and calculating the axial temperature gradient, g, at the radial position based on a predetermined critical v/G at the transition from interstitial-defects and the growth velocity, v, at which the transition from interstitial-defects was observed at the radial position in the test ingot.
Referring to claim 5-6, the combination of Wei et al and Hourai et al teaches a V/G is determine from the center to the periphery which would include R/2 (Hourai Fig 2-5).
Referring to claim 7, the combination of Wei et al and Hourai et al teaches growing an ingot, slicing and evaluating defects, which clearly suggests the growth velocity, v, at a given radial position of the test ingot at the transition from interstitial-defects is determined by vertical cut slabbing and observation of the slab to determine the position at which the transition from interstitial-defects occurs and determination of the growth velocity, v, at the position at which the transition from interstitial-defects occurs (Hourai col 7, ln 1-67 teaches pulled crystal, cut parallel to the axial direction of the crystal and examined for defect formation and Fig 4 depicts the distribution of defects).
Referring to claim 8, the combination of Wei et al and Hourai et al teaches the growth velocity, v, at a given radial position of the test ingot at the transition from interstitial-defects is determined by slicing wafers from the ingot and observation of the wafers to determine the position at which the transition from interstitial-defects occurs and determination of the growth velocity, v, at the position at which the transition from interstitial-defects occurs. (Wei CT [0080]-[0090] teaches the pulling speed V is gradually changed from high speed to low speed, and the COP region (void defect region), defect-free region, and dislocation cluster region are formed in the single crystal in sequence; and slicing wafers from the ingot in Fig 5).
Referring to claim 9, the combination of Wei et al and Hourai et al teaches a nitrogen concentration of 1x1014 to 5x1015 atoms/cm3 (Wei CT [0080]).
Referring to claim 10-13, the combination of Wei et al and Hourai et al teaches the rotation speed of the quartz crucible 11 is preferably 3 to 6 rpm so the main body of single-crystal silicon 3 be reduced to 1x1017 atoms/cm3 to 4x1017 atoms/cm3 (Wei CT [0075]-[0080]). Overlapping ranges are prima facie obvious (MPEP 2144.05).
Referring to claim 15, the combination of Wei et al and Hourai et al teaches horizontal magnetic field set 25 mm above the liquid surface, a crucible rotation speed of 0.1 rpm and magnetic field of 3500 G (~0.35 Tesla) (Wei CT [0084]).
Referring to claim 16, the combination of Wei et al and Hourai et al teaches producing defect-free silicon suitable for IGBT and avoiding gate oxide integrity failures (Wei CT [0005]); therefore, the wafers would be expected to be free of failures of a size greater than 8 MVcm.
Referring to claim 17, the combination of Wei et al and Hourai et al teaches batch growth (Wei CT [0083] teaches filling and not adding additional silicon).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al (CN 110863240), an English computer translation (CT) is provided, in view of Hourai et al (US 6,245,430), as applied to claim 1-13 and 15-17 above, and further in view of Basak et al (US 2016/0108551).
The combination of Wei et al and Hourai et al teaches all of the limitations of claim 14, as discussed above, except a cusp magnetic field is applied to the silicon melt; the crystal rotation rate is between 6 rpm and 15 rpm; the crucible rotation rate is between 0.5 rpm and 2.5 rpm; and the magnetic field strength is 0.02 and 0.075 Tesla at an edge of the silicon ingot at a melt-solid interface and between 0.05 and 0.20 Tesla at a wall of the crucible.
In a method of Czochralski crystal growth, Basak et al teaches applying a cusp magnetic field, wherein strength of the magnetic field is approximately 0.02 to 0.05 Tesla (T) at an edge of crystal 113 at the melt-solid interface and approximately 0.05 to 0.12 T at the wall of crucible 103 ([0042]). Basak et al also teaches teach a crystal rotation rate of 8 to 14 rpm [0050]-[0051]); and a crucible rotation rate of 1.3 to 2.2 rpm ([0039]-[0042]). Overlapping ranges are prima facie obvious (MPEP 2144.05). Basak et al also teaches by controlling conditions (i.e., heater power, crucible rotation, magnet strength, seed lift, melt to reflector gap, inert gas flow, inert gas pressure, seed rotation, and cusp position), a plurality of process parameters (i.e., a wall temperature of a crucible, a flow of SiO from the crucible to a single crystal, and an evaporation of SiO from a melt) are regulated to produce silicon ingots having a low oxygen concentration of less than 5 ppma ([0054]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Wei et al and Hourai et al by providing a cusp magnetic field is applied to the silicon melt; the crystal rotation rate is between 6 rpm and 15 rpm; the crucible rotation rate is between 0.5 rpm and 2.5 rpm; and the magnetic field strength is 0.02 and 0.075 Tesla at an edge of the silicon ingot at a melt-solid interface and between 0.05 and 0.20 Tesla at a wall of the crucible, as taught by Basak et al, by optimizing the processing parameters to obtain low oxygen concentration silicon ingots.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al (CN 110863240), an English computer translation (CT) is provided, in view of Hourai et al (US 6,245,430), as applied to claim 1-13 and 15-17 above, and further in view Hudson et al (US 2021/0079554).
The combination of Wei et al and Hourai et al teaches all of the limitations of claim 18, as discussed above, except the single crystal silicon ingot is grown in a continuous process in which silicon is added to the crucible during growth of the single crystal silicon ingot.
In a method of Czochralski crystal growth, Hudson et al teaches continuous Czochralski (CCZ) growth, polycrystalline silicon may be continually or periodically added to the molten silicon to replenish the melt during the growth process and, as a result, multiple ingots can be pulled from a single crucible during a growth process, wherein the traditional batch Czochralski growth chamber and apparatus are modified to include a means for feeding additional polycrystalline silicon to the melt in a continuous or semi-continuous fashion without adversely affecting the properties of the growing ingot ([0003]-[0004]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Wei et al and Hourai et al by growing in a continuous process in which silicon is added to the crucible during growth of the single crystal silicon ingot, as taught by Hudson et al, to pull multiple ingots from a single crucible during a growth process.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al (CN 110863240), an English computer translation (CT) is provided, in view of Hourai et al (US 6,245,430), as applied to claim 1-13 and 15-17 above, and further in view Nakazawa et al (US 2013/0260540).
The combination of Wei et al and Hourai et al teaches all of the limitations of claim 19, as discussed above, except singulation the wafer to produce a plurality of chips. The combination of Wei et al and Hourai et al teaches IGBTs have a structure with a PN junction for positive hole injection added to the MOSFET, and have three electrodes: emitter, collector, and gate; wherein the emitter is formed on the surface side of the silicon substrate (Wei CT [0004]). The combination of Wei et al and Hourai et al teaches forming IGBT from the wafer, however does not explicitly teach singulation the wafer to produce a plurality of chips.
In a method of device manufacturing, Nakazawa et al teaches a region of a wafer obtained from the crystal rod manufactured by the CZ method is cut into a plurality of semiconductor chips ([0055]-[0074]).
It would have been obvious to one of ordinary skill in the art at the time of filing to modify the combination of Wei et al and Hourai et al by singulating the wafer to produce a plurality of chips, as taught by Nakazawa et al, to producing a plurality of devices from a single wafer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sattler et al (US 2008/0187736) teaches a radial profile of a ratio V/G from the center to an edge of the phase boundary is controlled, G being the temperature gradient perpendicular to the phase boundary and V being the pull rate, wherein the radial profile of the ratio V/G is controlled so that the effect of thermomechanical stress in the single crystal adjoining the phase boundary, is compensated with respect to creation of intrinsic point defects to produce defect-free semiconductor wafers of silicon (Abstract; [0015], [0025]-[0038]).
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MATTHEW J. SONG
Examiner
Art Unit 1714
/MATTHEW J SONG/ Primary Examiner, Art Unit 1714