6 Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Election/Restrictions
Applicant’s election of species 1a (Fig. 2G-1), corresponding to claims 1-5, 8-10, 14-18, and 21-23 in the reply filed on 6/15/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). See the requirement for restriction/election filed on 4/20/2026 for details on why species are mutually exclusive.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s)
Claims 1, 2, 4, 5, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20070296079 A1; hereinafter Huang) in view of Tsuchiya et al. (JP 7061949 B2; hereinafter Tsuchiya).
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Annotated Fig. 6A - Huang
Regarding claim 1, Huang discloses:
An electronic package (Fig. 6A: referred to as heat sink package; [0046]), comprising:
a carrier structure (see annotated Fig. 6A: chip carrier structure 42; [0039]) having a circuit layer;
an electronic component disposed on the carrier structure (see annotated Fig. 6A: semiconductor chip 51, on the chip carrier structure 42; [0046]) and electrically connected to the circuit layer;
a heat sink disposed on the electronic component (Fig. 6A: heat slug 56; [0046]);
an encapsulation layer formed on the carrier structure and covering the electronic component and the heat sink (Fig. 6A: encapsulant 54, covering the semiconductor chip 51 and heat slug 56 from the sides); and
a heat dissipation structure having an opening and embedded in the encapsulation layer (see annotated Fig. 6A: first heat dissipating structure 45,; [0041] and [0045]), wherein
the heat sink is located in the opening (see annotated Fig. 6A: heat slug 56 located in the opening of the heat dissipation structure; [0046]).
Tsuchiya discloses the following claim limitations not disclosed by Huang:
a carrier structure having a circuit layer (Fig. 4: wiring layer WL1 arranged on the surface of wiring board PWB; pg. 33 [0046]);
an electronic component disposed on the carrier structure and electrically connected to the circuit layer (Fig. 4, semiconductor chip CHP1 is connected to other chips through wiring WL1a in the wiring layer WL1; page 33 [0048]);
Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date to combine the heat sink package of Huang with the wiring layer of Tsuchiya in order to provide a connection to other electronic components and external devices.
Regarding claim 2, Huang does not explicitly teach the electronic package of claim 1, wherein the electronic component is electrically connected to the circuit layer via a plurality of conductive bumps or a plurality of wires.
However, Huang does teach in Fig. 6A and paragraph 39, a plurality of conductive bumps, and in a separate embodiment, Fig. 7 and paragraph 47, teaches a plurality of wires not explicitly connected to the circuit layer.
However, Tsuchiya teaches wherein the electronic component is electrically connected to the circuit layer via a plurality of conductive bumps or a plurality of wires (Fig. 2 and 5: semiconductor chip CHP1 connected to wiring board PWB by electrode EL1 on the surface FS1, which can be a solder ball, and is also connected to the through the wiring WL1a on the wiring layer WL1 which is on FS1; [0019] and [0047]).
It would be obvious for one of ordinary skill in the art before the effective filing date to combine the heat sink device of Huang with the circuit layer of Tsuchiya in order to connect the electronic component to the circuit layer of the carrier structure and send and receive electrical signals from other components or external devices.
Regarding claim 4, Huang does not explicitly teach the electronic package of claim 1, wherein the heat sink is bonded to the electronic component via an adhesive material.
However, Tsuchiya teaches wherein the heat sink is bonded to the electronic component via an adhesive material (Fig. 2: adhesive AM2, connected between heat sink HS and semiconductor chip CHP1; page 32, [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the heat sink package of Huang with the adhesive of Tsuchiya in order to adhere the heat sink to the electronic component maintaining even heat dispersion without any shifting.
Regarding claim 5, Huang teaches the electronic package of claim 1, wherein an outer surface of the heat sink and an outer surface of the encapsulation layer are coplanar (Fig. 6A: heat slug 56 coplanar with top surface of the encapsulant 54).
Regarding claim 8, Huang teaches the electronic package of claim 1, wherein the electronic component is covered by the heat dissipation structure (see annotated Fig. 6A: heat dissipating structure 45 covers semiconductor chip 51 on the sides).
Regarding claim 9, Huang teaches the electronic package of claim 1, wherein the heat dissipation structure comprises a sheet-shaped body surrounding the heat sink (see annotated Fig. 6A: heat dissipating portion 451 surrounds heat slug 56 on the left and right; [0041]).
Regarding claim 10, Huang teaches the electronic package of claim 9, wherein the heat dissipation structure further comprises at least one supporting leg connected to the sheet-shaped body, and the supporting leg is bonded to the carrier structure (see annotated Fig. 6A: supporting leg portion 452 disposed on the carrier chip structure 42; [0042]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Tsuchiya as applied to claim 1 above, and further in view of Aoki et al. (JP 2008192714 A; hereinafter Aoki).
Regarding claim 3, Huang and Tsuchiya do not explicitly teach the electronic package of claim 1, wherein a width or an area of the heat sink is less than or equal to a width or an area of the electronic component.
However, Aoki teaches wherein a width or an area of the heat sink is less than or equal to a width or an area of the electronic component (Fig. 1: heat sink 17 is smaller than the size of semiconductor chip 12; page 11, [0010]).
Aoki also teaches in paragraphs 5 – 8 that a larger heat sink produces stress generated as a result of the difference in thermal expansion between the heat sink and the semiconductor chip causing cracks to form in the sealing resin, and that a smaller heat sink can help to minimize that occurrence.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the heat sink package of Huang with the heat sink of Aoki in order to mitigate the amount of cracks forms in the encapsulation.
Claims 14, 15, 17, 18, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20070296079 A1; hereinafter Huang) in view of Tsuchiya et al. (JP 7061949 B2; hereinafter Tsuchiya).
Regarding claim 14, Huang discloses:
A method of manufacturing an electronic package, comprising:
providing a carrier structure (see annotated Fig. 6A: chip carrier structure 42; [0039]) having a circuit layer;
disposing an electronic component (see annotated Fig. 6A: semiconductor chip 51, on the chip carrier 42; [0046]) and
a heat dissipation structure having an opening on the carrier structure (see annotated Fig. 6A: first heat dissipating structure 45 has an opening between the ends of the sheet shaped body; [0041] and [0045]), wherein
the electronic component is electrically connected to the circuit layer (see annotated Fig. 6A: stated to be electrically connected to the chip carrier 42 through conductive bumps 410, but not explicitly stated to be connected to the circuit layer; [0039]), wherein
a position of the opening corresponds to the electronic component (see annotated Fig. 6A: opening is formed above the semiconductor chip 51; [0044]), and
the electronic component is correspondingly exposed from the opening (see annotated Fig. 6A: recess structure formed in the encapsulant to expose the top surface of semiconductor chip 51 where the heat slug 56 is placed; [0044]);
disposing at least one heat sink in the opening and on the electronic component (Fig. 6A: heat slug 56; [0046]); and
forming an encapsulation layer on the carrier structure to cover the electronic component, the heat dissipation structure and the heat sink (see annotated Fig. 6A: encapsulant 54, covering the semiconductor chip 51, heat dissipating structure 45 and heat slug 56 from the sides; [0042]).
Tsuchiya discloses the following claim limitations not disclosed by Huang:
providing a carrier structure having a circuit layer (Fig. 4: wiring layer WL1 arranged on the surface of wiring board PWB; pg. 33 [0046]);
the electronic component is electrically connected to the circuit layer (Fig. 4, semiconductor chip CHP1 is connected to other chips through wiring WL1a in the wiring layer WL1; page 33 [0048]);
Therefore, it would be obvious for one of ordinary skill in the art before the effective filing date to combine the heat sink package of Huang with the wiring layer of Tsuchiya in order to provide a connection to other electronic components and external devices.
Regarding claim 15, Huang does not explicitly teach the method of claim 14, wherein the electronic component is electrically connected to the circuit layer via a plurality of conductive bumps or a plurality of wires.
However, Huang does teach in Fig. 6A and paragraph 39, a plurality of conductive bumps, and in a separate embodiment, Fig. 7 and paragraph 47, teaches a plurality of wires not explicitly connected to the circuit layer.
However, Tsuchiya teaches wherein the electronic component is electrically connected to the circuit layer via a plurality of conductive bumps or a plurality of wires (Fig. 2 and 5: semiconductor chip CHP1 connected to wiring board PWB by electrode EL1 on the surface FS1, which can be a solder ball, and is also connected to the through the wiring WL1a on the wiring layer WL1 which is on FS1; [0019] and [0047]).
It would be obvious for one of ordinary skill in the art before the effective filing date to combine the heat sink device of Huang with the circuit layer of Tsuchiya in order to use bumps or wires to connect the electronic component to the circuit layer of the carrier structure and send and receive electrical signals from other components or external devices.
Regarding claim 17, Huang does not explicitly teach the method of claim 14, wherein the heat sink is bonded to the electronic component via an adhesive material.
However, Tsuchiya teaches wherein the heat sink is bonded to the electronic component via an adhesive material (Fig. 2: adhesive AM2, connected between heat sink HS and semiconductor chip CHP1; page 32, [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the heat sink package of Huang with the adhesive of Tsuchiya in order to adhere the heat sink to the electronic component maintaining even heat dispersion without any shifting.
Regarding claim 18, Huang teaches the method of claim 14, wherein an outer surface of the heat sink and an outer surface of the encapsulation layer are coplanar (Fig. 6A: heat slug 56 coplanar with top surface of the encapsulant 54).
Regarding claim 21, Huang teaches the method of claim 14, wherein the electronic component is covered by the heat dissipation structure (see annotated Fig. 6A: heat dissipating element 45 covers semiconductor chip 51 on both sides).
Regarding claim 22, Huang teaches the method of claim 14, wherein the heat dissipation structure comprises a sheet shaped body surrounding the heat sink. (see annotated Fig. 6A: heat dissipating portion 451 surrounds heat slug 56 on the left and right; [0041]).
Regarding claim 23, Huang teaches he method of claim 22, wherein the heat dissipation structure further comprises at least one supporting leg connected to the sheet-shaped body, and the supporting leg is bonded to the carrier structure (see annotated Fig. 6A: supporting portion 452 disposed on the carrier chip 42; [0042]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Tsuchiya as applied to claim 14 above, and further in view of Aoki et al. (JP 2008192714 A; hereinafter Aoki).
Regarding claim 16, Huang and Tsuchiya do not explicitly teach the method of claim 14, wherein a width or an area of the heat sink is less than or equal to a width or an area of the electronic component.
However, Aoki teaches wherein a width or an area of the heat sink is less than or equal to a width or an area of the electronic component (Fig. 1: heat sink 17 is smaller than the size of semiconductor chip 12; page 11, [0010]).
Aoki also teaches in paragraphs 5 – 8 that a larger heat sink produces stress generated as a result of the difference in thermal expansion between the heat sink and the semiconductor chip causing cracks to form in the sealing resin, and that a smaller heat sink can help to minimize that occurrence.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the heat sink package of Huang with the heat sink of Aoki in order to mitigate the amount of cracks forms in the encapsulation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN HOANG TRAN whose telephone number is (571)270-0290. The examiner can normally be reached 8am-6pm.
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/BENJAMIN HOANG TRAN/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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