Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the amendment filled on 6/22/2026 that has been entered, wherein claims 1-14 and 21-26 are pending and claims 15-20 are canceled.
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-14 and 21-26 in the reply filed on 6/22/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/12/2024 and 1/22/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 7 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Horita et al. (US 2006/0214212 A1).
Regarding claim 1, Horita teaches a device(Fig. 23), comprising:
a memory-cell circuit(memory cell, Fig. 3, ¶0031); and
a non-memory-cell circuit(logic circuit, ¶0031) that includes an active region(1a, 1b, ¶0079);
wherein:
the active region(1a, 1b, ¶0079) extends in a first direction(direction perpendicular to line C-C) in a top view;
the active region(1a, 1b, ¶0079) includes a first segment(1b, ¶0079) and a second segment(1a, ¶0079);
the first segment(1b, ¶0079) has a first dimension(WB, ¶0079) measured in a second direction(direction of line C-C) in the top view;
the second segment(1a, ¶0079) has a second dimension(WA, ¶0079) measured in the second direction(direction of line C-C) different from the first direction(direction perpendicular to line C-C) in the top view; and
the second dimension(WA, ¶0079) is different(¶0079) from the first dimension(WB, ¶0079).
Regarding claim 2, Horita teaches the device of claim 1, wherein the non-memory-cell circuit(logic circuit, ¶0031) includes an input-output circuit, a driver circuit for the memory-cell circuit(memory cell, Fig. 3, ¶0031), a control circuit, or a logic circuit(logic circuit, ¶0031).
Regarding claim 4, Horita teaches the device of claim 1, wherein:
the active region(1a, 1b, ¶0079) is a first active region(1a, 1b, ¶0079);
the memory-cell circuit(memory cell, Fig. 3, ¶0031) has a plurality of second active regions(1d, ¶0079); and
the second active regions(1d, ¶0079) have substantially similar dimensions(WD, ¶0079) in the second direction(direction of line C-C).
Regarding claim 7, Horita teaches the device of claim 1, wherein: the active region(1a, 1b, ¶0079) includes two or more branches(1a, 1b, ¶0079) that each extends in the first direction(direction perpendicular to line C-C); and
the first segment(1b, ¶0079) or the second segment(1a, ¶0079) is located in one of the branches(1a, 1b, ¶0079).
Regarding claim 10, Horita teaches the device of claim 1, wherein the active region(1a, 1b, ¶0079) is a part of a vertically-protruding structure(14, Fig. 25) of a FinFET device(Fig. 24) or a gate-all-around (GAA) device.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3 and 22-25 are rejected under 35 U.S.C. 103 as being unpatentable over Horita et al. (US 2006/0214212 A1) in view of Matsui (US 2017/0148488 A1).
Regarding claim 3, Horita teaches the device of claim 1, wherein:
the first segment(1b, ¶0079) of the active region(1a, 1b, ¶0079) is a part of a first transistor(TR2, ¶0035) having a first speed(inherent);
the second segment(1a, ¶0079) of the active region(1a, 1b, ¶0079) is a part of a second transistor(TR1, ¶0035) having a second speed(inherent); and
the second dimension(WA, ¶0079) is greater(¶0079) than the first dimension(WB, ¶0079).
Horita is not relied on to teach a second speed(inherent) faster than the first speed.
Matsui teaches a device(Fig. 10) wherein a second speed(speed of first input transistor 1021, ¶0032, ¶0035) faster than the first speed(speed of second input transistors 1022,¶0032, ¶0035). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Horita, so that a second speed faster than the first speed, as taught by Matsui, in order to facilitate reading of the data(¶0033).
Regarding claim 22, Horita teaches a device, comprising:
a first type of circuit(eSRAM, ¶0031); and
a second type of circuit(logic circuit, ¶0031) that includes a semiconductor structure(1a, 1b, ¶0079, ¶0081) that protrudes vertically upwards in a cross-sectional side view(Fig. 24); wherein:
the semiconductor structure(1a, 1b, ¶0079, ¶0081) is oriented along a first horizontal direction(direction perpendicular to line C-C) in a top view that is defined by the first horizontal direction(direction perpendicular to line C-C) and a second horizontal direction(direction of line C-C) perpendicular to the first horizontal direction(direction perpendicular to line C-C);
the semiconductor structure(1a, 1b, ¶0079, ¶0081) includes a first segment(1a, ¶0079) that is a part of a first transistor(TR1, ¶0035) and a second segment(1b, ¶0079) that is a part of a second transistor(TR2, ¶0035);
and
the first segment(1a, ¶0079) is wider(¶0079) than the second segment(1b, ¶0079) in the second horizontal direction(direction of line C-C) in the top view.
Horita is not relied on to teach the first transistor(TR1, ¶0035) is faster than the second transistor(TR2, ¶0035) in operation.
Matsui teaches a device(Fig. 10) wherein a first transistor(first input transistor 1021, ¶0032, ¶0035) is faster(¶0035, ¶0035) than the second transistor(second input transistors 1022, ¶0032, ¶0035). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Horita, so that a second speed faster than the first speed, as taught by Matsui, in order to facilitate reading of the data(¶0033).
Regarding claim 23, Horita teaches the device of claim 22, wherein:
the first type of circuit(eSRAM, ¶0031) includes a memory cell(eSRAM, ¶0031); and
the second type of circuit(logic circuit, ¶0031) includes an input-output circuit, a driver circuit for the memory cell, a control circuit, or a logic circuit(logic circuit, ¶0031).
Regarding claim 24, Horita teaches the device of claim 22, wherein:
the semiconductor structure(1a, 1b, ¶0079, ¶0081) is a first semiconductor structure(1a, 1b, ¶0079, ¶0081);
the first type of circuit(eSRAM, ¶0031) has a plurality of second semiconductor structures(1d, ¶0079); and
the second semiconductor structures(1d, ¶0079) have substantially similar dimensions(WD, ¶0079) in the second horizontal direction(direction of line C-C) in the top view.
Regarding claim 25, Horita teaches the device of claim 22, wherein:
the semiconductor structure(1a, 1b, ¶0079, ¶0081) includes two or more branches(1a, 1b, ¶0079, ¶0081) that each extends in the first horizontal direction; and
the first segment(1b, ¶0079) or the second segment(1a, ¶0079) is located in one of the branches(1a, 1b, ¶0079, ¶0081).
Allowable Subject Matter
Claims 5-6, 8, 9 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claim 5, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “the first edge and the third edge are substantially flush with each other; and
a jog exists in the second direction between the second edge and the fourth edge”.
Regarding dependent claim 6, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “a first jog exists in the second direction between the first edge and the third edge; and
a second jog exists in the second direction between the second edge and the fourth edge.”
Regarding dependent claim 8, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “the second segment is directly abutting the two or more branches in the first direction; and
the active region further includes a third segment that is directly abutting the second segment in the first direction”.
Claim 9 depends on claim 8 and inherits it’s allowable subject matter.
Regarding dependent claim 26, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “the first segment, the second segment, and the third segment are misaligned with one another in the second horizontal direction”.
Claims 11-14 and 21 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 11, Horita teaches a device, comprising:
a static random access memory (SRAM) cell array(eSRAM, ¶0031); and
a non-SRAM circuit(logic circuit, ¶0031) that includes an active region(1a, 1b, ¶0079) that extends in a first direction(direction perpendicular to line C-C) in a top view;
wherein:
the active region(1a, 1b, ¶0079) includes a first segment(1a, ¶0079) and a second segment(1b, ¶0079);
the first segment(1a, ¶0079) is a part of a first transistor(TR1, ¶0035) and has a first dimension(WA, ¶0079) in a second direction(direction of line C-C) in a top view, the second direction(direction of line C-C) being perpendicular to the first direction(direction perpendicular to line C-C);
the second segment(1b, ¶0079) is a part of a second transistor(TR2, ¶0035) and has a second dimension(WB, ¶0079) in the second direction(direction of line C-C) in the top view;
and
the first dimension(WA, ¶0079) is greater(¶0079) than the second dimension(WB, ¶0079).
Horita does not disclose a second segment(1b, ¶0079) directly abutting the first segment(1a, ¶0079), the first transistor(TR1, ¶0035) is faster than the second transistor(TR2, ¶0035).
Matsui teaches a device(Fig. 10) wherein a first transistor(first input transistor 1021, ¶0032, ¶0035) is faster(¶0035, ¶0035) than the second transistor(second input transistors 1022, ¶0032, ¶0035). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Horita, so that a second speed faster than the first speed, as taught by Matsui, in order to facilitate reading of the data(¶0033).
Horita and Matsui do not disclose a second segment(1a, ¶0079) directly abutting the first segment(1b, ¶0079).
Regarding independent claim 11, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “a second segment directly abutting the first segment”.
Claims 12-14 and 21 depend on claim 11 and are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
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/LAURA M DYKES/Examiner, Art Unit 2892
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