DETAILED ACTION
This Office Action is in response to Application filed on January 12, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species D, drawn to the embodiment shown in Figs. 6A-6D, in the reply filed on June 16, 2026 is acknowledged. The traversal is on the ground(s) that the Applicant prefers not to limit the scope of any claims to the elected Species and/or Invention. This is not found persuasive because Applicants' preference of not being limited to the elected species is not a legal standard of a Restriction Requirement. Rather, a legal ground of a Restriction Requirement is based on 35 USC 101, which stipulates that one patent should correspond to one invention. The requirement is still deemed proper and is therefore made FINAL.
Claims 8 and 18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species A and C, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on June 16, 2026.
Claim Objections
Claim 15 is objected to because of the following informalities:
On line 2 of claim 15, the meaning of the acronym “MOSFET” should be typed out before the acronym because the meaning of acronyms can change over time.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7, 12-17, 19, and 59 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 2, 6-7, 12, 16-17, and 19 are rendered as indefinite because they recite the term “inactive region”, which is unclear because if Applicants claim a power semiconductor device, then all of the features on the device are active to a certain degree and under certain operating conditions. What do Applicants mean by “inactive region”? Does this depend on specific operating conditions? Or is it always inactive under any circumstances?
Claims 2-7 and 12-15 depend on claim 1, and claims 17 and 19 depend on claim 16, and therefore, claims 2-7, 12-15, 17, and 19 are also indefinite.
Regarding claim 1, Applicants do not claim “a semiconductor” before claiming “the semiconductor”, and therefore, the limitation “the semiconductor” lacks the antecedent basis.
Claims 2-7 and 12-15 depend on claim 1, and therefore, claims 2-7 and 12-15 are also indefinite.
Regarding claims 1 and 3, the limitation “a gate insulating electric field” is rendered as indefinite because it is unclear what it means. What applicants claim depends on how gate insulating electric field is generated. Displacement current is variable depending on operating conditions. What operating conditions do Applicants claim? Is there only one displacement current under the claimed operating conditions? Or do Applicants claim the gate insulating electric field for all of the possible displacement currents? How can you measure the electric field in the gate insulating pattern, which is a dielectric?
Claims 2-7 and 12-15 depend on claim 1, and therefore, claims 2-7 and 12-15 are also indefinite.
Regarding claims 2, 19, and 59, Applicants do not claim “a field insulating layer” before claiming “field insulating layer” and therefore, the limitation “field insulating layer” lacks the antecedent basis.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, 12-17, 19, and 59 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sundaresan et al. (US 20220367640 A1) hereinafter referred to as “Sundaresan”.
Regarding claim 1, as best understood, Sundaresan discloses a power semiconductor device (Fig. 21ff), comprising: a semiconductor structure (elements B901, B902, B905, and B910); a polysilicon gate layer (element B915) on the semiconductor structure (elements B901, B902, B905, and B910) in an inactive region of the semiconductor device; a gate insulating pattern (element B914) between the polysilicon gate layer (element B915) and the semiconductor structure (elements B901, B902, B905, and B910), the gate insulating pattern (element B914) having a thickness such that a distance between the semiconductor in the inactive region and the polysilicon gate layer through the gate insulating pattern is less than about 100 nm ([0321]); a shunt contact structure (shown in annotated Fig. 21ff) on semiconductor structure (elements B901, B902, B905, and B910) in the inactive region, the shunt contact structure (shown in annotated Fig. 21ff) providing a path for a displacement current from a drain contact (element B921, shown in annotated Fig. 21ff) to a source contact (element B921, shown in annotated Fig. 21ff) through the semiconductor structure (elements B901, B902, B905, and B910) in the inactive region; and wherein a gate insulating electric field across the gate insulating pattern (element B914) associated with the displacement current is less than about 8 MV/cm.
Regarding claim 2, Sundaresan discloses the power semiconductor device of claim 1, wherein there is no field insulating layer having a thickness of greater than about 100 nm between the polysilicon gate layer (element B915) and the semiconductor structure (elements B901, B902, B905, and B910) in the inactive region of the semiconductor structure (elements B901, B902, B905, and B910).
Regarding claim 3, Sundaresan discloses the power semiconductor device of claim 1, wherein the polysilicon gate layer (element B915) is located in a region proximate the shunt contact structure (shown in annotated Fig. 21ff) such that the gate insulating electric field resulting from the displacement current is less than about 8 MV/cm.
Regarding claim 4, Sundaresan discloses the power semiconductor device of claim 1, further comprising a gate pad (element B921, shown in annotated Fig. 21ff) coupled to the polysilicon gate layer (element B915) with at least one gate via (shown in annotated Fig. 21ff), wherein the polysilicon gate layer (element B915) has an area that is less than about 25% of an area of the gate pad (element B921, shown in annotated Fig. 21ff).
Regarding claim 5, Sundaresan discloses the power semiconductor device of claim 4, wherein the power semiconductor device comprises a plurality of gate vias (shown in annotated Fig. 21ff) and a plurality of shunt contact structures (shown in annotated Fig. 21ff), wherein the plurality of gate vias (shown in annotated Fig. 21ff) and the plurality of shunt contact structures (shown in annotated Fig. 21ff) are interdigitated.
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Regarding claim 6, Sundaresan discloses the power semiconductor device of claim 4, further comprising an inter metal dielectric (IMD) layer (element B917) between at least a portion of the gate pad (element B921, shown in annotated Fig. 21ff) and the semiconductor structure (elements B901, B902, B905, and B910) in the inactive region.
Regarding claim 7, Sundaresan discloses the power semiconductor device of claim 6, wherein the IMD layer (element B917) directly contacts at least a portion of the gate pad (element B921, shown in annotated Fig. 21ff) and at least a portion of the semiconductor structure (elements B901, B902, B905, and B910) in the inactive region.
Regarding claim 12, Sundaresan discloses the power semiconductor device of claim 1, wherein a distance between the semiconductor structure (elements B901, B902, B905, and B910) in the inactive region and the polysilicon gate layer (element BB915) through the gate insulating pattern (element B914) is less than about 50 nm ([0321]).
Regarding claim 13, Sundaresan discloses the power semiconductor device of claim 1, wherein the semiconductor structure (elements B901, B902, B905, and B910) is a wide bandgap semiconductor structure ([0318]).
Regarding claim 14, Sundaresan discloses the power semiconductor device of claim 13, wherein the wide bandgap semiconductor structure (elements B901, B902, B905, and B910) comprises silicon carbide ([0318]).
Regarding claim 15, Sundaresan discloses the power semiconductor device of claim 1, wherein the power semiconductor device is a MOSFET (Fig. 21ff)..
Regarding claim 16, as best understood, Sundaresan discloses a power semiconductor device (Fig. 21ff), comprising: a semiconductor structure (elements B901, B902, B905, and B910); a polysilicon gate layer (element B915) on the semiconductor structure (elements B901, B902, B905, and B910) in an inactive region of the power semiconductor device; a gate pad (element B921, shown in annotated Fig. 21ff) coupled to the polysilicon gate layer (element B915); an inter metal dielectric (IMD) layer (element B917) between at least a portion of a gate pad (element B921, shown in annotated Fig. 21ff) and the semiconductor structure (elements B901, B902, B905, and B910) in the inactive region; and wherein the IMD layer (element B917) directly contacts at least a portion of the gate pad (element B921, shown in annotated Fig. 21ff) and at least a portion of the semiconductor structure (elements B901, B902, B905, and B910) in the inactive region.
Regarding claim 17, Sundaresan discloses the power semiconductor device of claim 16, further comprising a gate insulating pattern (element B914) in the inactive region between the polysilicon gate layer (element B915) and the semiconductor structure (elements B901, B902, B905, and B910).
Regarding claim 19, Sundaresan discloses the power semiconductor device of claim 16, wherein there is no field insulating layer having a thickness of greater than about 100 nm between the polysilicon gate layer (element B915) and the semiconductor structure (elements B901, B902, B905, and B910) in the inactive region of the semiconductor structure (elements B901, B902, B905, and B910).
Regarding claim 59, as best understood, Sundaresan discloses a power semiconductor device (Fig. 21ff), comprising: a semiconductor structure (elements B901, B902, B905, and B910); a polysilicon gate layer (element B915); a gate insulating pattern (element B914) between the polysilicon gate layer (element B915) and the semiconductor structure (elements B901, B902, B905, and B910); a shunt contact structure (shown in annotated Fig. 21ff), the shunt contact structure (shown in annotated Fig. 21ff) providing a path for a displacement current from a drain contact (element B921, shown in annotated Fig. 21ff) to a source contact (element B921, shown in annotated Fig. 21ff); and wherein there is no field insulating layer having a thickness of greater than 100 nm between the polysilicon gate layer (element B915) and the semiconductor structure (elements B901, B902, B905, and B910).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANGELICA ROSE E. GALVAN whose telephone number is (571)270-0122. The examiner can normally be reached Monday - Friday 8:30am - 6:00pm ET.
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/ANGELICA ROSE GALVAN/Examiner, Art Unit 2815
/JAY C KIM/Primary Examiner, Art Unit 2815
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