Last updated: July 17, 2026

Application No. 18/412,567

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Non-Final OA

Filed

Jan 14, 2024

Examiner

HARRISTON, WILLIAM A

Art Unit

2899

Tech Center

2800 — Semiconductors & Electrical Systems

Assignee

Taiwan Semiconductor Manufacturing Company, Ltd.

OA Round

1 (Non-Final)

Interview Optional

— +8.2% interview lift. Interview already conducted in this application's prosecution history. This examiner has a 89% grant rate with +8.2% interview lift. Since an interview has already been tried, recommend written response with narrowed claims based on precedent claim evolution patterns.

Based on 1066 resolved cases, 2023–2026

Examiner Intelligence

HARRISTON, WILLIAM A View full profile →

Grants 89% — above average

Career Allowance Rate

953 granted / 1066 resolved

+21.4% vs TC avg

Moderate +8% lift

Without

With

+8.2%

Interview Lift

resolved cases with interview

Typical timeline

2y 2m

Avg Prosecution

16 currently pending

Career history

1089

Total Applications

across all art units

Statute-Specific Performance

§101

0.2%

-39.8% vs TC avg

§103

65.6%

+25.6% vs TC avg

§102

11.5%

-28.5% vs TC avg

§112

1.0%

-39.0% vs TC avg

Black line = Tech Center average estimate • Based on career data from 1066 resolved cases

Prosecution Timeline

Jan 14, 2024

Application Filed

Apr 08, 2026

Non-Final Rejection mailed

May 14, 2026

Interview Requested

May 22, 2026

Applicant Interview (Telephonic)

May 22, 2026

Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

17/987,132

Patent 12677641

SEMICONDUCTOR DEVICE

3y 7m to grant Granted Jul 07, 2026

18/357,728

Patent 12672568

SUBSTRATE HAVING AN INCREASED METAL TRACE THICKNESS

2y 11m to grant Granted Jun 30, 2026

17/898,398

Patent 12660564

PRINT-READY WAFERS WITH BOTTOM-ANCHORED COMPONENTS

3y 9m to grant Granted Jun 16, 2026

17/710,490

Patent 12653001

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND PATTERN FORMATION METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES

4y 2m to grant Granted Jun 09, 2026

18/215,830

Patent 12648497

SEMICONDUCTOR PACKAGE USING SUBSTRATE BLOCK INTEGRATION

2y 11m to grant Granted Jun 02, 2026

Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.

Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2

Expected OA Rounds

89%

Grant Probability

98%

With Interview (+8.2%)

2y 2m (~0m remaining)

Median Time to Grant

Low

PTA Risk

Based on 1066 resolved cases by this examiner. Grant probability derived from career allowance rate.