DETAILED ACTION
This Office Action is in response to Application filed on January 14, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Invention II and Species B drawn to a semiconductor device as recited in claim 8 and Subspecies ii drawn to the embodiments shown in Fig. 5, claims 8-9, 12, and 14-15, and newly added claims 21-27, in the reply filed on May 19, 2026 is acknowledged.
Claim Objections
Claim 9 is objected to because of the following informalities:
On line 9 of claim 21, the word “structure” should be inserted after “the first dielectric”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-9, 12, 14-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 8 and 12 are rendered as indefinite because they recite the term “redistribution structure” which is not clearly defined by the claims or the original disclosure, and the specification does not provide a standard for ascertaining the requisite degree, i.e. what kind of a structure can be referred to as a “redistribution structure”. Thus, one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. In other words, the term “redistribution structure” is unclear because it is unclear what is being redistributed by the structure (Is it redistributing current, electrical power, a magnetic field, an electric field, migrating impurities, incident photons, etc.?). For purposes of examination, the term “redistribution structure” is interpreted by the Examiner as “structure”.
The limitation “wherein at least one of the plurality of metal patterns comprises a conductive structure electrically connected with the semiconductor substrate” recited in claim 8 is indefinite because Applicants cannot claim that both of the conductive structures are electrically connected to the substrate because if this was true, then they would be shorted. There are two conductive structures 330M, and 330(300M). If these two conductive structures are electrically connected to the substrate, then the device would be shorted, rendering the claimed semiconductor device inoperative.
Claims 9, 14, and 15 depend on claim 8, and therefore, claims 9, 14, and 15 are also indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8-9, 12, 14-15, and 21-27, as best understood, are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (US 2022/0359449 A1) hereinafter referred to as “Chen”.
Regarding claim 8, as best understood, Chen discloses a semiconductor device (Fig. 14), comprising: a semiconductor substrate (element 131) ([0021]); a redistribution structure (element 132) ([0021]) disposed above the semiconductor substrate (element 131), wherein the redistribution structure comprises a plurality of metal patterns (element 134), wherein at least one of the plurality of metal patterns (element 134, see Fig. 14a) ([0029]) comprises a conductive structure (element 134, see Fig. 14b) electrically connected with the semiconductor substrate (element 131); and a plurality of dummy dielectric pillars (element 135, see Fig. 14c) ([0032]), dispersed in the conductive structure (element 134) and completely surrounded laterally by the conductive structure (element 134), because Applicants do not specifically claim what the “dummy dielectric pillars” refer to, and therefore, the “dummy dielectric pillars” can be interpreted to be directed to a product by process limitation.
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Regarding claim 9, Chen discloses the semiconductor device of claim 8 (Fig. 14), further comprises: a metal liner (element 133), disposed on and in contact with the conductive structure (element 134) and at least a portion of the plurality of dummy dielectric pillars (element 135); and a conductive terminal (element 180), disposed on the metal liner (element 170).
Regarding claim 12, Chen discloses the semiconductor device of claim 8 (Fig. 14), wherein the redistribution structure (element 132) further comprises: a conductive feature (element 132b), wherein the conductive feature is embedded in a first dielectric layer (132a) underlying the conductive structure (element 134), and the conductive structure (element 134) is electrically connected with the conductive feature (element 132b), wherein the conductive feature (132b) is a conductive via or a conductive line (paragraph [0027]).
Regarding claim 14, Chen discloses the semiconductor device of claim 8 (Fig. 14), wherein the conductive structure (element 134) is electrically connected with a transistor of the semiconductor substrate (element 131, paragraph [0023]).
Regarding claim 15, Chen discloses the semiconductor device of claim 8 (Fig. 14), wherein the plurality of dummy dielectric pillars (element 135) have a same width.
Regarding claim 21, Chen discloses a semiconductor device (Fig. 14), comprising: a substrate (element 131); and a wiring structure , disposed above the substrate, wherein the wiring structure (element 132) comprises: a first dielectric structure (element 132a); a conductive feature (element 132b) embedded in the first dielectric structure (element 132a); a second dielectric structure (element 135), disposed above the first dielectric structure (element 132a) and comprising a plurality of dummy pillars (element 135, see Fig. 14c) and a main portion (element 135, see Fig. 14d); and a metal pattern (element 134), disposed above the first dielectric (132a) and comprising a conductive structure (element 134) electrically connected with the conductive feature (element 132b), wherein the plurality of dummy pillars (element 135) are embedded in the conductive structure (element 134), and the main portion (element 135) surrounds the conductive structure (element 134).
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Regarding claim 22, Chen discloses the semiconductor device of claim 21 (Fig. 14), wherein a top surface of the conductive structure (element 134) is aligned with top surfaces of the plurality of dummy pillars (element 135).
Regarding claim 23, Chen discloses the semiconductor device of claim 21 (Fig. 14), further comprising: an etch stop layer (element 135, paragraph [0032]), wherein the metal pattern (element 134), the plurality of dummy pillars (element 135) and the main portion (element 135) are in contact with the etch stop layer (element 135, paragraph [0032]).
Regarding claim 24, Chen discloses the semiconductor device of claim 21 (Fig. 14), further comprising a conductive terminal (element 180), wherein the conductive terminal is overlapped with and electrically connected to the conductive structure (element 134).
Regarding claim 25, Chen discloses the semiconductor device of claim 21 (Fig. 14), wherein a thickness of the main portion (element 135) is larger than or equal to a thickness of the plurality of dummy pillars (element 135).
Regarding claim 26, Chen discloses the semiconductor device of claim 21, wherein the plurality of dummy pillars have a same width (element 135).
Regarding claim 27, Chen discloses the semiconductor device of claim 21, wherein the plurality of dummy pillars (element 135) are arranged in an array along a first direction and a second direction perpendicular to the first direction (element 130A, Fig. 15 and 16).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANGELICA ROSE E. GALVAN whose telephone number is (571)270-0122. The examiner can normally be reached Monday - Friday 8:30am - 6:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/ANGELICA ROSE GALVAN/Examiner, Art Unit 2815
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