DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims read by species A,C,D,E, and F in the reply filed on June 3, 2026 are acknowledged. The traversal is on the ground(s) that claims 1-4 and 15-20 are generic claims. This is found persuasive because these claims read on elected species B. The traversal is also on the grounds that claims 5-7 and 12-14 are allowable because they depend from a generic claims 1-4 and 15-20. This is not found persuasive because the search burden for embodiments drawn on non-elected species still exists. The specific limitations of species A, C, D, E, and F would require different fields of search. The requirement is deemed proper and is therefore made FINAL.
Claims 5-7, and 12-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species A, C, D, E, and F, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on June 3, 2026.
Specification
The disclosure is objected to because of the following informalities: Figure 1 referenced in the spec ¶0024, speaks on semiconductor die 110 and 111, these are not features in figure 1. Appropriate correction is required. Specification description for figure one should read “semiconductor die 120 and 121”.
Claim Objections
Claim 17 objected to because of the following informalities: “and an frame portion”. Appropriate correction is required. Claim should read “ and a frame portion”.
Claim 2 is objected to because of the following informalities: “wherein a number of the at least one die”. Appropriate correction is required. Claim should read “ wherein a number of at least one semiconductor die”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitation "frame portion" in a lid comprising a plate portion and an frame portion protruding from the plate portion. There is insufficient antecedent basis for this limitation in the claim. In this instant case, the frame portion mentioned in claims 1-16 refer to the frame portion of cavity 2.
Claims 18-20 depend on claim 17, and are rejected under 35 USC 112(b) for implicitly including the indefinite subject matter above.
For the purposes of compact prosecution, the Examiner has interpreted claim 17 such that the frame portion of the lid refers to a “lid frame portion”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,2,8, 11, 15, and 16 are rejected under U.S.C 102(a)(2) as being anticipated by Chen et. Al. (PG PUB No. US 20210305227 A1).
Regarding claim 1, Chen teaches A semiconductor device (¶0044 fig 10a-c), comprising:
a substrate; a lid (¶0064 fig 10c: lid 300, made up of 330a-c and 210/220) attached to the substrate (¶0044, fig 10c:100), wherein the lid (¶0048, fig 10 c: lid 300, includes 330 and stiffeners 210/220) has a first cavity (see annotated fig 10c) and a second cavity (¶0061, fig 10c: 335) extending from the first cavity (annotated fig 10c) to inside of the lid;
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a semiconductor package (fig 10c: 130, molded die 132) disposed in the first cavity, below the second cavity (fig 10c: 335) and electrically connected to the substrate (¶0045 package connected to 100 by solder bumps), wherein the semiconductor package (¶0045 fig 10c: 130, molded die 132) comprises at least one semiconductor die, and the second cavity (fig 10c: 335) is disposed adjacent to periphery of at least one semiconductor die (¶064, fig 10c: 132) in a top view of the semiconductor device (fig 10a: 132 and 335 are disposed adjacent to 120 in a top view); and
a thermal conductive bonding layer (¶0046 fig 10c: 170, thermal interface material) attaching the lid to the semiconductor package (fig 10c: 130, molded die 132) and extending into at least a portion of the second cavity (fig 10c: 170 attaches 300 composite lid to 132 and extending into 335).
Regarding claim 2, Chen teaches the semiconductor device (¶0044 fig 10a-c), as claimed in claim 1, wherein a number of the at least one die is plural (¶0044 fig 10a: there are more than one 132), the second cavity comprises a frame portion (fig 10a: portion of 335 around the perimeter of 130) and a branch portion (fig 10a: portion of 335 extending between 132) located in and connected to the frame portion (fig 10a: portion of 335 around the perimeter of 130, and portion of 335 extending between 132 are connected) , and wherein:
the plurality of semiconductor dies (fig 10a : 132) are surrounded by the frame portion (fig 10a: portion of 335 around the perimeter of 130), and two adjacent semiconductor dies among the plurality of semiconductor dies (fig 10a: 132) are separated by the branch portion in the top view of the semiconductor device (fig 10a: 132 are separated by inner edge of 335 in the top view of 150).
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Regarding claim 8, Chen teaches the semiconductor device as claimed in claim 2, wherein the thermal conductive bonding layer (¶0061 fig 10c: 170) further extends into the frame portion (fig 10c: portion of 335 around the perimeter of 130) of the second cavity (fig 10c: 335) (fig 10c: 170 extends into 335).
Regarding claim 11, Chen teaches the semiconductor device as claimed in claim 8, wherein a contact angle of the thermal conductive bonding layer (¶0061, fig 10c: 170 TIM) overlapped with the frame portion (fig 10c: portion of 335 around the perimeter of 130) is 30° to 150° (170 overlapped with edge of 132 fills 335 at a 90° angle, which is between 30° and 150°).
Regarding claim 15. Chen teaches a semiconductor device (¶0044 fig 10a-c), comprising:
a substrate (fig 10c:100);
a lid attached to the substrate, wherein the lid (¶0048, fig 10c: lid 300, including 330a-c and 210/220) has a first cavity (annotated, fig 10c: cavity 1) and a second cavity (annotated fig 10c: 335) extending from the first cavity to inside of the lid (fig 10c: 300 has cavity 1 and cavity 2 extends from cavity 1 into 330a);
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a semiconductor package (fig 10c: 130, including molded die 132) disposed in the first cavity (132 disposed in cavity 1) and electrically connected to the substrate (¶0045, 130 disposed in cavity 1 and electrically connected to the substrate by solder bumps), wherein the semiconductor package comprises at least one semiconductor die (fig 10a: 132), and the at least one semiconductor die (fig 10a: 132) is surrounded by the second cavity (fig 10c: 335) in a top view (fig 10a: 132 is surrounded by 335) of the semiconductor device ((¶0044 fig 10a, top view); and
a thermal conductive bonding layer (¶0061, fig 10c: 170 TIM) attaching the lid (¶0048, fig 10c: 330) to the semiconductor package (fig 10c: 130, including molded die 132) and extending into at least a portion of the second cavity (fig 10c: 335) (¶0048, fig 10c: 170 attaching 330 to 132 and extends into 335).
Regarding claim 16, Chen teaches the semiconductor device as claimed in claim 15, wherein the at least one semiconductor die (fig 10a: 130) comprises a first semiconductor die (fig 10a: 132) and second semiconductor dies (fig 10a: 132), and the second cavity (fig 10a: 335) comprises a frame portion (fig 10: portion of 335 around the perimeter of 130) and a branch portion (fig 10: portion of 335 extending between 132) located in and connected to the frame portion (335 comprises a outer edge and an inner edge where the inner edge is connected to the outer edge), and wherein:
the first semiconductor die (fig 10a: 132) and the second semiconductor dies (fig 10a: 132), are surrounded by the frame portion ( fig 10a: both die 132 are surrounded by portion of 335 around the perimeter of 130), and the second semiconductor dies are separated by the branch portion in the top view of the semiconductor device (fig 10a: both die 132 are separated by portion of 335 extending between 132),
a lateral distance between the frame portion at least one of the first semiconductor die and the second semiconductor dies is 0 to 0.4mm (Chen teaches 335 overlapping edges of 132, and at least the midpoint of 335 is arranged directly above edges of die 132, meeting the broadest reasonable interpretation of 0mm offset),
a lateral distance between the branch portion and at least one of the second semiconductor dies is 0 to 0.4mm (Chen teaches frame portion 335 is shown positioned directly above edges of 132, then stands to reason that branch portion of 335 would also be directly above edges of 132).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (Pg Pub. No. US 20210305227 A1).
Regarding claim 3, Chen teaches the semiconductor device (fig 10c) as claimed in claim 2, wherein the frame portion (fig 10: portion of 335 around the perimeter of 130) and the branch (fig 10: portion of 335 extending between 132)
Chen does not teach the frame portion and the branch portion are overlapped with an encapsulant of the semiconductor package.
However, Chen does teach an alternate embodiment figure 2a that teaches a semiconductor package where the semiconductor die (¶0045: 132) are overlapped with an encapsulant (¶0045 fig 2a: 134 molding compound) of the semiconductor package (¶0045, fig 2a: 130).
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to configure the semiconductor package of Chen with the encapsulant of embodiment 2a to fill a space laterally between the semiconductor dies to relieve high stress locations (¶0064). In the instant case, the frame and branch are located above the semiconductor package, therefore because the semiconductor package is encapsulated the branch and frame portions are located above the encapsulant.
Regarding claim 4, Chen teaches the semiconductor device as claimed in claim 2, wherein two adjacent memory dies (fig 10a: 132) among the plurality of semiconductor dies are separated by the branch portion (fig 10a: portion of 335 extending between 132) in the top view of the semiconductor device.
Chen does not explicitly teach the two adjacent memory dies among the plurality of semiconductor die are memory die.
However, Chen does teach a semiconductor device with both memory components (¶0044, fig 1:120) and logic components (¶0044, fig 1: 130). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to reconfigure the memory chips to maximize the number of components in the semiconductor device. In this instant case, the configuration of semiconductor chips can be memory or logic chips and assembling chips in a different order does not result in a different function for the semiconductor device.
Claim 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Ho et. al. (Pg Pub No. US 20150187679 A1).
Regarding claim 9, Chen teaches the semiconductor device as claimed in claim 8, wherein the thermal conductive bonding layer is overlapped with the frame portion.
Chen does not explicitly teach wherein a thickness of the thermal conductive bonding layer overlapped with the frame portion (fig 10: portion of 335 around the perimeter of 130) is 0.2mm to 1mm.
Ho teaches a thickness (¶0029, fig 2C:T’)of the thermal conductive bonding layer(¶0027, fig 2A-2C)) overlapped with the frame portion (fig 2A: 24’) is 0.01mm to 2.5mm (¶0027-¶0029, fig 2A-2C: thickness of 28’ overlapped with 24’ is T’).
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to configure the semiconductor device taught by Galloway in view of Eid with the thickness of thermal conductive bonding layer overlapped with the frame portion in Ho as means to create maximum contact surface area and prevent direct contact between the lid and device die(¶0029 ).
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, determining the optimum or workable ranges involves only routine skill in the art. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). In the instant case, modifying the thickness of thermal conductive bonding layer to arrive at the claimed thickness “0.02 mm to 1 mm” would be a matter of routine optimization.
Regarding claim 10, Chen teaches the semiconductor device as claimed in claim 8,
Chen does not explicitly teach wherein a width of the thermal conductive bonding layer corresponding to the frame portion is 1mm to 2mm.
Ho teaches a semiconductor device wherein the width of the thermal conductive bonding layer (¶0029, fig 2C:28’ TIM) corresponding to the frame portion (¶0029: 24’ top of lid) is 0.15 mm.
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to optimize the width of the thermal conductive bonding layer to improve package integrity, and heat dissipation efficiency (Ho ¶0032).
The specification contains no disclosure of either the critical nature of the claimed [values/ranges] nor any unexpected results arising therefrom. "The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. . . . In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range." In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). To establish unexpected results over a claimed range, applicants should compare a sufficient number of tests inside and outside the claimed range to show criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197(CCPA 1960).
Claim(s) 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Urago (Pg Pub. No. US 20160035637 A).
Regarding claim 17, Chen teaches a semiconductor device (fig 10a-c), comprising:
a substrate (fig 10c:100);
a lid (fig 10c: 300 and component 210/220) comprising a plate portion (¶0064, fig 10c:330a-c) and an frame portion (fig 10c:210) protruding from the plate portion towards the substrate (¶0064, fig 10c: 300 comprises 330a-c and 210/220 protruding from 330a-c towards 100), wherein the plate portion (fig 10c:330a-c) and the frame portion (fig 10c:210) form a first cavity facing the substrate (fig 10c:100), and the plate portion has a second cavity extending from the first cavity to inside of the plate portion (fig 10c:330a-c);
a semiconductor package (fig 10c: molded die 132) disposed in the first cavity, below the second cavity, electrically connected to the substrate (132 disposed in cavity 1, below cavity 2, electrically connected to 100 by solder bumps);
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and a thermal conductive bonding layer (fig 10c: 170 TIM) disposed on the semiconductor package (fig 10a: 130, comprised of molded die 132) (170 disposed on
130), and extending into at least a portion of the second cavity.
Chen does not teach a first adhesive bonding the frame portion to the substrate;
a second adhesive bonding the plate portion to the substrate,
and semiconductor package laterally surrounded by the second adhesive,
and the Thermal conductive bonding layer laterally surrounded by the second adhesive.
Urago teaches a first adhesive (fig 4: 24) bonding the frame portion (fig 4: 23 sidewall) to the substrate (¶0054, fig 4: 2);
a second adhesive (¶0055, fig 4: 31 conductive member) bonding the plate portion (¶0058 fig 4: 21) to the substrate( fig 4: 2) (¶0045 24 bonding 23 to 2 31 bonding 21 to 2 by way of 22);
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and semiconductor package (¶0044 fig 4: 3 and its connecting components) laterally surrounded by the second adhesive (¶0055, fig 4: 31 conductive member) (fig 4: 3 laterally surrounded by 31)
and the Thermal conductive bonding (¶0045, fig 4: 13) layer laterally surrounded by the second adhesive (¶0055, fig 4: 31 conductive member) (13 is laterally surrounded by 31 on 2 side).
It would have been obvious to one of the ordinary skill in the art at the time the invention was filed to configure the semiconductor package of Chen with the use of two adhesives of Urago to improve lid connectivity and reduce warpage (Urago ¶0049). In this instant case, the semiconductor package is located inside the sub cavity page by the lid and structure 22/31/14, therefor these items are laterally located next to each other.
Regarding claim 18, Chen in view of Urago teaches the semiconductor device as claimed in claim 17, further comprising:
an underfill (Urago ¶0045, fig 4: 12) disposed between the semiconductor package (¶0044 fig 4: 3 and its connecting components) and the substrate (fig 4: 2) and laterally surrounded by the second adhesive (¶0055, fig 4: 31 conductive member) (12 disposed between 3 and 2 and laterally surrounded by 31).
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Urago as applied to claim 17 above , and further view of Kanayama et. Al. (Pg Pub. No. US 20080185712 A1).
Regarding claim 19, Chen in view of Urago teaches the semiconductor device as claimed in claim 17, wherein:
the first cavity (Urago fig 4: cavity 1 ) is separated by the second adhesive (Urago fig 4: 31 conductive member) into a first sub cavity (Urago annotated fig 4: sub cavity 1) in which the semiconductor package (¶0044 fig 4: 3 and its connecting components) is disposed and a second sub cavity (Urago annotated fig 4: sub cavity 2) located between the first sub cavity ( Urago fig 4: sub cavity 1) and the frame portion (¶0045, fig 4: 23 sidewall member),
the second sub cavity (fig 4: sub cavity 2) and external of the semiconductor device (outside the semiconductor device).
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Chen and Urago does not teach second sub cavity and external of the semiconductor device are in gas communication via a first gas discharge hole of the first adhesive, and the first sub cavity and the second sub cavity are in gas communication via a second gas discharge hole of the second adhesive.
Kanayama teaches a gas discharge hole (¶0075: vent hole) in the adhesive layer (fig 7B: 82).
It would have been obvious to one of ordinary skill in the art at the time the
invention was filed to configure the semiconductor device of ref 1 , the first and second adhesives of ref 2, and the gas communication through gas discharge holes of adhesives of ref 3 to prevent damage when the air in the cavities expands (¶0076). Furthermore, the repetition or creation of more than one adhesive with a gas discharge hole is routine optimization to increase the ability to release pressure throughout the device.
Allowable Subject Matter
Claim 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 20, Chen in view of Urago and Kanyama teach a semiconductor device as claimed in claim 19,
Chen in view of Urago and Kanyama teach there is a first and second adhesive with vent holes located in them.
However, Chen in view of Urago and Kanyama do not explicitly teach wherein the second gas discharge hole is higher than the first gas discharge hole.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LYTESHIA M PRICE whose telephone number is (571)270-0132. The examiner can normally be reached 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LYTESHIA M PRICE/
Examiner, Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
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